Cross Reference: /drivers/tty/serial/meson

Lines Matching refs:membase
102 	val = readl(port->membase + AML_UART_STATUS);
110 	val = readl(port->membase + AML_UART_CONTROL);
112 	writel(val, port->membase + AML_UART_CONTROL);
119 	val = readl(port->membase + AML_UART_CONTROL);
121 	writel(val, port->membase + AML_UART_CONTROL);
133 	val = readl(port->membase + AML_UART_CONTROL);
136 	writel(val, port->membase + AML_UART_CONTROL);
151 	while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
153 			writel(port->x_char, port->membase + AML_UART_WFIFO);
163 		writel(ch, port->membase + AML_UART_WFIFO);
181 		status = readl(port->membase + AML_UART_STATUS);
191 			mode = readl(port->membase + AML_UART_CONTROL);
193 			writel(mode, port->membase + AML_UART_CONTROL);
197 			writel(mode, port->membase + AML_UART_CONTROL);
206 		ch = readl(port->membase + AML_UART_RFIFO);
215 	} while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
228 	if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
231 	if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL))
249 	val = readl(port->membase + AML_UART_CONTROL);
251 	writel(val, port->membase + AML_UART_CONTROL);
254 	writel(val, port->membase + AML_UART_CONTROL);
257 	writel(val, port->membase + AML_UART_CONTROL);
260 	writel(val, port->membase + AML_UART_CONTROL);
263 	writel(val, port->membase + AML_UART_MISC);
275 	while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_EMPTY))
278 	val = readl(port->membase + AML_UART_REG5);
282 	writel(val, port->membase + AML_UART_REG5);
298 	val = readl(port->membase + AML_UART_CONTROL);
337 	writel(val, port->membase + AML_UART_CONTROL);
373 		iounmap(port->membase);
374 		port->membase = NULL;
398 		port->membase = devm_ioremap_nocache(port->dev,
401 		if (port->membase == NULL)
437 	if (!port->membase)
440 	while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
442 	writel(ch, port->membase + AML_UART_WFIFO);
485 	if (!port || !port->membase)