Cross Reference: /drivers/tty/serial/mxs-auart.c

Lines Matching refs:membase
284 	while (!(readl(s->port.membase + AUART_STAT) &
289 				     s->port.membase + AUART_DATA);
296 				     s->port.membase + AUART_DATA);
306 			     s->port.membase + AUART_INTR_CLR);
309 			     s->port.membase + AUART_INTR_SET);
321 	c = readl(s->port.membase + AUART_DATA);
322 	stat = readl(s->port.membase + AUART_STAT);
357 	writel(stat, s->port.membase + AUART_STAT);
365 		stat = readl(s->port.membase + AUART_STAT);
371 	writel(stat, s->port.membase + AUART_STAT);
407 	u32 ctrl = readl(u->membase + AUART_CTRL2);
418 	writel(ctrl, u->membase + AUART_CTRL2);
424 	u32 stat = readl(u->membase + AUART_STAT);
425 	int ctrl2 = readl(u->membase + AUART_CTRL2);
448 	stat = readl(s->port.membase + AUART_STAT);
455 	writel(stat, s->port.membase + AUART_STAT);
519 		s->port.membase + AUART_CTRL2_CLR);
574 	ctrl2 = readl(u->membase + AUART_CTRL2);
664 	writel(ctrl, u->membase + AUART_LINECTRL);
665 	writel(ctrl2, u->membase + AUART_CTRL2);
675 					u->membase + AUART_INTR_CLR);
687 	u32 stat = readl(s->port.membase + AUART_STAT);
689 	istat = readl(s->port.membase + AUART_INTR);
696 			s->port.membase + AUART_INTR_CLR);
701 				s->port.membase + AUART_INTR_CLR);
724 	writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
727 		reg = readl(u->membase + AUART_CTRL0);
732 	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
744 	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
746 	writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
749 			u->membase + AUART_INTR);
758 	writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
770 	writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
773 			u->membase + AUART_INTR_CLR);
775 	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
782 	if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
793 	writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
800 	writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
805 	writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
812 			     u->membase + AUART_LINECTRL_SET);
815 			     u->membase + AUART_LINECTRL_CLR);
843 	while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
849 	writel(ch, port->membase + AUART_DATA);
869 	old_ctrl2 = readl(port->membase + AUART_CTRL2);
870 	old_ctrl0 = readl(port->membase + AUART_CTRL0);
873 		     port->membase + AUART_CTRL0_CLR);
875 		     port->membase + AUART_CTRL2_SET);
880 	while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
892 	if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) {
893 		writel(old_ctrl0, port->membase + AUART_CTRL0);
894 		writel(old_ctrl2, port->membase + AUART_CTRL2);
906 	if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
909 	lcr_h = readl(port->membase + AUART_LINECTRL);
924 	quot = ((readl(port->membase + AUART_LINECTRL)
927 	quot |= ((readl(port->membase + AUART_LINECTRL)
1062 	s->port.membase = ioremap(r->start, resource_size(r));
1088 	version = readl(s->port.membase + AUART_VERSION);