Lines Matching defs:aty_ld_le32

569 #define aty_ld_le32(regindex)		_aty_ld_le32(regindex, par)
586 return aty_ld_le32(CLOCK_CNTL_DATA);
637 val = aty_ld_le32(BIOS_0_SCRATCH);
640 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
643 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
661 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
678 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
702 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
708 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
719 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
724 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
726 aty_ld_le32(GEN_RESET_CNTL);
728 aty_ld_le32(GEN_RESET_CNTL);
841 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
845 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
1015 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
1303 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
1305 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
1308 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
1320 reg = aty_ld_le32(LVDS_GEN_CNTL);
1331 reg = aty_ld_le32(LVDS_GEN_CNTL);
1349 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1535 config = aty_ld_le32(CNFG_CNTL) & ~3;
1685 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) |
1690 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
1800 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1816 aty_ld_le32(LVDS_GEN_CNTL);
1830 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1839 aty_ld_le32(LVDS_GEN_CNTL);
1845 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1944 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
2046 dac = aty_ld_le32(DAC_CNTL);
2054 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2133 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2399 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2400 save_dp_cntl = aty_ld_le32(DP_CNTL);
2457 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &