Cross Reference: /drivers/video/fbdev/aty/mach64

Lines Matching refs:pll
17 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
18 static int aty_dsp_gt       (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
19 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
20 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
119 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll)
126 	multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real;
127 	divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
129 	ras_multiplier = pll->xclkmaxrasdelay;
135 	vshift = (6 - 2) - pll->xclk_post_div;	/* FIFO is 64 bits wide in accelerator mode ... */
141 	if (pll->xres != 0) {
145 		divider = divider * pll->xres & ~7;
148 		ras_divider = ras_divider * pll->xres & ~7;
159 	tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
172 	dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
183 		dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift);
199 	pll->dsp_on_off = (dsp_on << 16) + dsp_off;
200 	pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks;
203 		__func__, pll->dsp_config, pll->dsp_on_off);
208 static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll)
215 	q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
220 		pll->vclk_post_div  = (q < 128*8);
221 		pll->vclk_post_div += (q <  64*8);
222 		pll->vclk_post_div += (q <  32*8);
224 	pll->vclk_post_div_real = postdividers[pll->vclk_post_div];
225 	//    pll->vclk_post_div <<= 6;
226 	pll->vclk_fb_div = q * pll->vclk_post_div_real / 8;
227 	pllvclk = (1000000 * 2 * pll->vclk_fb_div) /
228 		(par->ref_clk_per * pll->pll_ref_div);
231 		__func__, pllvclk, pllvclk / pll->vclk_post_div_real);
233 	pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
237 		int ecp = pllvclk / pll->vclk_post_div_real;
244 		pll->pll_vclk_cntl |= ecp_div << 4;
250 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll)
255 	if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
257 	if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
259 	/*aty_calc_pll_ct(info, &pll->ct);*/
263 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll)
267 	ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
269 	if(pll->ct.xres > 0) {
271 		ret /= pll->ct.xres;
280 void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll)
291 		pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
295 		par->clk_wr_offset, pll->ct.vclk_fb_div,
296 		pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
313 	aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
319 	tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
326 	tmp |= pll->ct.pll_ext_cntl;
331 	aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
333 	aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
336 	aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
339 	aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
340 	aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
358 		aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
359 		aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
376 static void aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll)
383 	pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
385 	pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
386 	pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
387 	pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
388 	pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
390 	pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
391 	pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
394 		pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
395 		pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
399 static int aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll)
408 	pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
409 	pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
410 	pll->ct.xclk_ref_div = 1;
411 	switch (pll->ct.xclk_post_div) {
416 		pll->ct.xclk_ref_div = 3;
417 		pll->ct.xclk_post_div = 0;
421 		printk(KERN_CRIT "atyfb: Unsupported xclk source:  %d.\n", pll->ct.xclk_post_div);
424 	pll->ct.mclk_fb_mult = 2;
425 	if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
426 		pll->ct.mclk_fb_mult = 4;
427 		pll->ct.xclk_post_div -= 1;
432 		__func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
438 	pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
439 	pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
442 		pll->ct.fifo_size = 32;
444 		pll->ct.fifo_size = 24;
445 		pll->ct.xclkpagefaultdelay += 2;
446 		pll->ct.xclkmaxrasdelay += 3;
452 			pll->ct.dsp_loop_latency = 10;
454 			pll->ct.dsp_loop_latency = 8;
455 			pll->ct.xclkpagefaultdelay += 2;
461 			pll->ct.dsp_loop_latency = 9;
463 			pll->ct.dsp_loop_latency = 8;
464 			pll->ct.xclkpagefaultdelay += 1;
469 			pll->ct.dsp_loop_latency = 11;
471 			pll->ct.dsp_loop_latency = 10;
472 			pll->ct.xclkpagefaultdelay += 1;
476 		pll->ct.dsp_loop_latency = 8;
477 		pll->ct.xclkpagefaultdelay += 3;
480 		pll->ct.dsp_loop_latency = 11;
481 		pll->ct.xclkpagefaultdelay += 3;
485 	if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
486 		pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
495 		pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
504 			pll->ct.fifo_size = 32;
506 			pll->ct.fifo_size = 24;
513 		pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
515 		pll->ct.xclk_post_div_real = postdividers[pll_ext_cntl & 0x07];
519 		pll->ct.mclk_fb_div = mclk_fb_div;
523 	pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
526 	q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
527 		(pll->ct.mclk_fb_mult * par->xclk_per);
537 	pll->ct.xclk_post_div_real = postdividers[xpost_div];
538 	pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
543 		pll->ct.xclk_post_div = xpost_div;
544 		pll->ct.xclk_ref_div = 1;
549 	pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
550 			(par->ref_clk_per * pll->ct.pll_ref_div);
552 		__func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
556 		pll->ct.pll_gen_cntl = OSC_EN;
558 		pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
561 		pll->ct.pll_ext_cntl = 0;
563 		pll->ct.pll_ext_cntl = xpost_div;
565 	if (pll->ct.mclk_fb_mult == 4)
566 		pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
569 		pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
575 		pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
577 		q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
587 		pll->ct.sclk_fb_div = q * sclk_post_div_real / 8;
588 		pll->ct.spll_cntl2 = mpost_div << 4;
590 		pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) /
591 			(par->ref_clk_per * pll->ct.pll_ref_div);
598 	pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
599 	pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC);
605 			      union aty_pll *pll)
617 		aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
618 		aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
626 	aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
627 	aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
628 	aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
629 	aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
630 	aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);