Lines Matching refs:rinfo
40 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo);
98 static int radeon_apply_workarounds(struct radeonfb_info *rinfo)
103 if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) &&
104 (id->subsystem_device == rinfo->pdev->subsystem_device )) {
110 rinfo->pm_mode |= id->pm_mode_modifier;
113 rinfo->reinit_func = id->new_reinit_func;
121 static inline int radeon_apply_workarounds(struct radeonfb_info *rinfo)
129 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
134 if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
135 if (rinfo->has_CRTC2) {
152 if (!rinfo->has_CRTC2) {
165 if (rinfo->family == CHIP_FAMILY_RV350) {
231 if (rinfo->is_mobility) {
248 else if (rinfo->family == CHIP_FAMILY_R300 ||
249 rinfo->family == CHIP_FAMILY_R350) {
260 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
274 if (rinfo->is_IGP) {
285 else if (rinfo->is_mobility) {
303 if (rinfo->is_mobility) {
330 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
335 if (!rinfo->has_CRTC2) {
350 if (rinfo->family == CHIP_FAMILY_RV350) {
420 if (rinfo->vram_width == 64) {
435 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
472 if ((rinfo->family == CHIP_FAMILY_RV250 &&
474 ((rinfo->family == CHIP_FAMILY_RV100) &&
482 if ((rinfo->family == CHIP_FAMILY_RV200) ||
483 (rinfo->family == CHIP_FAMILY_RV250) ||
484 (rinfo->family == CHIP_FAMILY_RV280)) {
489 if (((rinfo->family == CHIP_FAMILY_RV200) ||
490 (rinfo->family == CHIP_FAMILY_RV250)) &&
500 if (((rinfo->family == CHIP_FAMILY_RV200) ||
501 (rinfo->family == CHIP_FAMILY_RV250)) &&
527 if (rinfo->is_mobility) {
549 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
555 static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
561 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
563 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
564 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
565 rinfo->save_regs[2] = INPLL(MCLK_CNTL);
566 rinfo->save_regs[3] = INPLL(SCLK_CNTL);
567 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
568 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
569 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
570 rinfo->save_regs[7] = INPLL(MCLK_MISC);
571 rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
573 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
574 rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
575 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
576 rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
577 rinfo->save_regs[14] = INREG(BUS_CNTL1);
578 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
579 rinfo->save_regs[16] = INREG(AGP_CNTL);
580 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
581 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
582 rinfo->save_regs[19] = INREG(GPIOPAD_A);
583 rinfo->save_regs[20] = INREG(GPIOPAD_EN);
584 rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
585 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
586 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
587 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
588 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
589 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
590 rinfo->save_regs[27] = INREG(GPIO_MONID);
591 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
593 rinfo->save_regs[29] = INREG(SURFACE_CNTL);
594 rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
595 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
596 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
597 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
599 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
600 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
601 rinfo->save_regs[36] = INREG(BUS_CNTL);
602 rinfo->save_regs[39] = INREG(RBBM_CNTL);
603 rinfo->save_regs[40] = INREG(DAC_CNTL);
604 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
605 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
606 rinfo->save_regs[38] = INREG(FCP_CNTL);
608 if (rinfo->is_mobility) {
609 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
610 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
611 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
612 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
613 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
614 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
615 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
618 if (rinfo->family >= CHIP_FAMILY_RV200) {
619 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
620 rinfo->save_regs[46] = INREG(MC_CNTL);
621 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
622 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
623 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
624 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
625 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
626 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
627 rinfo->save_regs[53] = INREG(MC_DEBUG);
629 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
630 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
631 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
632 rinfo->save_regs[57] = INREG(FW_CNTL);
634 if (rinfo->family >= CHIP_FAMILY_R300) {
635 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
636 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
637 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
638 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
639 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
640 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
641 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
642 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
643 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
644 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
645 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
646 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
647 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
648 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
649 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
650 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
652 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
653 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
654 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
655 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
656 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
657 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
660 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
661 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
662 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
663 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
664 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
665 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
666 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
668 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
669 rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
670 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
671 rinfo->save_regs[84] = INREG(TMDS_CNTL);
672 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
673 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
674 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
675 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
676 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
677 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
678 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
679 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
680 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
681 rinfo->save_regs[96] = INREG(HDP_DEBUG);
682 rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
683 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
684 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
687 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
689 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
691 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
692 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
693 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
694 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
695 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
696 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
697 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
698 OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
699 if (rinfo->family == CHIP_FAMILY_RV350)
700 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
702 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
703 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
704 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
705 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
706 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
707 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
709 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
710 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
711 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
712 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
713 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
714 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
715 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
716 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
717 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
718 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
719 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
721 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
722 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
723 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
724 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
725 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
726 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
727 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
728 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
729 OUTREG(GPIO_MONID, rinfo->save_regs[27]);
730 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
733 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
747 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
750 if (rinfo->family <= CHIP_FAMILY_RV280) {
752 __INPLL(rinfo, pllPIXCLKS_CNTL)
777 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
782 if (rinfo->family <= CHIP_FAMILY_RV280) {
821 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
862 if (rinfo->family <= CHIP_FAMILY_RV280)
962 if (rinfo->family <= CHIP_FAMILY_RV280) {
1059 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
1063 mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
1065 mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
1068 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
1070 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
1073 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1074 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1079 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
1083 mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
1085 mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
1088 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
1090 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
1093 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1094 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1099 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
1133 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1146 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1193 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1203 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1244 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1265 if (rinfo->family == CHIP_FAMILY_RV350) {
1266 u32 sdram_mode_reg = rinfo->save_regs[35];
1288 radeon_pm_enable_dll_m10(rinfo);
1289 radeon_pm_yclk_mclk_sync_m10(rinfo);
1292 if (rinfo->of_node != NULL) {
1295 mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size);
1308 radeon_pm_m10_program_mode_wait(rinfo);
1326 else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1338 radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1339 radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1340 radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1349 else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1360 radeon_pm_enable_dll(rinfo);
1363 radeon_pm_yclk_mclk_sync(rinfo);
1366 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1367 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1368 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1369 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1370 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1379 else if (rinfo->is_mobility) {
1393 radeon_pm_enable_dll(rinfo);
1396 radeon_pm_yclk_mclk_sync(rinfo);
1399 if (rinfo->family <= CHIP_FAMILY_RV250) {
1400 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1401 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1402 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1403 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1404 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1407 else if (rinfo->family == CHIP_FAMILY_RV280) {
1408 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1409 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1410 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1432 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1457 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1471 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1482 radeon_pll_errata_after_index(rinfo);
1484 radeon_pll_errata_after_data(rinfo);
1488 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1508 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1517 radeon_pll_errata_after_index(rinfo);
1519 radeon_pll_errata_after_data(rinfo);
1523 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1542 tmp |= rinfo->save_regs[2] & 0xffff;
1549 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1567 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1578 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1591 OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1594 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1595 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1603 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1619 OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1620 OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1633 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1638 radeon_pll_errata_after_index(rinfo);
1640 radeon_pll_errata_after_data(rinfo);
1647 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1656 radeon_pll_errata_after_index(rinfo);
1658 radeon_pll_errata_after_data(rinfo);
1663 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1683 radeon_pll_errata_after_index(rinfo);
1684 radeon_pll_errata_after_data(rinfo);
1687 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1689 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1690 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1691 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1693 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1694 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1695 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1696 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1697 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1698 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1699 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1701 OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1702 OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1703 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1704 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1705 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1706 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1707 OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1708 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1709 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1710 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1711 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1712 OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1713 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1714 OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1715 OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1716 OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1720 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1725 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1726 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1727 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1728 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1729 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1730 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1731 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1732 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1733 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1734 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1735 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1736 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1744 radeon_pm_reset_pad_ctlr_strength(rinfo);
1750 radeon_pm_all_ppls_off(rinfo);
1768 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1769 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1770 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1773 tmp = rinfo->save_regs[1]
1778 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1779 OUTREG(FW_CNTL, rinfo->save_regs[57]);
1780 OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1781 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1782 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1783 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1786 radeon_pm_m10_reconfigure_mc(rinfo);
1800 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1803 tmp = rinfo->save_regs[2] & 0xff000000;
1852 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1853 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1854 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1857 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1858 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1859 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1860 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1863 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1866 OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
1872 OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
1889 radeon_pm_start_mclk_sclk(rinfo);
1892 radeon_pm_full_reset_sdram(rinfo);
1907 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
1908 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
1911 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
1913 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
1915 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
1918 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
1919 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
1920 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
1924 writeb(0, rinfo->fb_base + i);
1931 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
1932 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
1935 radeon_pm_m10_disable_spread_spectrum(rinfo);
1936 radeon_pm_restore_pixel_pll(rinfo);
1942 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
1948 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
1950 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1951 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1952 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1954 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1955 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1956 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1957 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1958 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1959 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1960 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1962 OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
1963 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
1964 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
1965 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
1966 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
1967 OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
1969 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1974 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
1979 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
1980 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1981 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1982 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1983 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1984 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1985 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1986 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1987 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1988 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1989 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1991 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1995 radeon_pm_reset_pad_ctlr_strength(rinfo);
2001 radeon_pm_all_ppls_off(rinfo);
2018 OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
2020 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
2021 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
2022 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
2024 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2025 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
2026 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2028 tmp = rinfo->save_regs[1]
2033 OUTREG(FW_CNTL, rinfo->save_regs[57]);
2040 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
2043 tmp = rinfo->save_regs[2] & 0xff000000;
2082 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
2083 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
2084 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
2087 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
2088 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
2091 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
2092 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
2101 tmp = rinfo->save_regs[0];
2118 radeon_pm_m9p_reconfigure_mc(rinfo);
2121 radeon_pm_start_mclk_sclk(rinfo);
2124 radeon_pm_full_reset_sdram(rinfo);
2139 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2140 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2147 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2148 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2149 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2155 tmp |= rinfo->save_regs[34] & 0xffff0000;
2160 tmp |= rinfo->save_regs[34] & 0xffff0000;
2164 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2167 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2172 writeb(0, rinfo->fb_base + i);
2175 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2176 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2188 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2192 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
2193 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2200 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2201 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2204 radeon_pm_m10_disable_spread_spectrum(rinfo);
2205 radeon_pm_restore_pixel_pll(rinfo);
2206 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2212 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2219 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2220 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2221 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2222 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2223 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2224 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2240 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2241 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2242 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2243 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2245 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2247 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2277 radeon_pll_errata_after_index(rinfo);
2279 radeon_pll_errata_after_data(rinfo);
2300 radeon_pll_errata_after_index(rinfo);
2302 radeon_pll_errata_after_data(rinfo);
2343 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2345 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2348 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2350 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2366 OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2368 OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2371 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
2373 radeon_pm_full_reset_sdram(rinfo);
2385 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2386 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2387 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2430 radeon_pll_errata_after_index(rinfo);
2432 radeon_pll_errata_after_data(rinfo);
2449 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2454 radeon_pll_errata_after_index(rinfo);
2456 radeon_pll_errata_after_data(rinfo);
2459 radeon_pll_errata_after_index(rinfo);
2461 radeon_pll_errata_after_index(rinfo);
2462 radeon_pll_errata_after_data(rinfo);
2517 static void radeonfb_whack_power_state(struct radeonfb_info *rinfo, pci_power_t state)
2522 pci_read_config_word(rinfo->pdev,
2523 rinfo->pdev->pm_cap + PCI_PM_CTRL,
2528 pci_write_config_word(rinfo->pdev,
2529 rinfo->pdev->pm_cap + PCI_PM_CTRL,
2533 rinfo->pdev->current_state = state;
2536 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2540 if (!rinfo->pdev->pm_cap)
2549 pci_name(rinfo->pdev));
2554 radeon_pm_disable_dynamic_mode(rinfo);
2557 radeon_pm_save_regs(rinfo, 0);
2561 if (rinfo->is_mobility) {
2563 radeon_pm_program_v2clk(rinfo);
2566 radeon_pm_disable_iopad(rinfo);
2569 radeon_pm_low_current(rinfo);
2572 radeon_pm_setup_for_suspend(rinfo);
2574 if (rinfo->family <= CHIP_FAMILY_RV280) {
2585 pci_disable_device(rinfo->pdev);
2586 pci_save_state(rinfo->pdev);
2591 radeonfb_whack_power_state(rinfo, PCI_D2);
2592 __pci_complete_power_transition(rinfo->pdev, PCI_D2);
2595 pci_name(rinfo->pdev));
2597 if (rinfo->family <= CHIP_FAMILY_RV250) {
2599 radeon_pm_full_reset_sdram(rinfo);
2602 radeon_pm_restore_regs(rinfo);
2605 radeon_pm_restore_regs(rinfo);
2607 radeon_pm_full_reset_sdram(rinfo);
2615 struct radeonfb_info *rinfo = info->par;
2641 radeonfb_engine_reset(rinfo);
2646 radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2649 rinfo->asleep = 1;
2650 rinfo->lock_blank = 1;
2651 del_timer_sync(&rinfo->lvds_timer);
2669 if (rinfo->pm_mode & radeon_pm_off) {
2676 radeon_pm_disable_dynamic_mode(rinfo);
2678 radeon_pm_save_regs(rinfo, 1);
2680 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2695 if (rinfo->pm_mode & radeon_pm_d2)
2696 radeon_set_suspend(rinfo, 1);
2706 static int radeon_check_power_loss(struct radeonfb_info *rinfo)
2708 return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) ||
2709 rinfo->save_regs[2] != INPLL(MCLK_CNTL) ||
2710 rinfo->save_regs[3] != INPLL(SCLK_CNTL);
2716 struct radeonfb_info *rinfo = info->par;
2722 if (rinfo->no_schedule) {
2737 if ((rinfo->pm_mode & radeon_pm_off) && radeon_check_power_loss(rinfo)) {
2738 if (rinfo->reinit_func != NULL)
2739 rinfo->reinit_func(rinfo);
2751 else if (rinfo->pm_mode & radeon_pm_d2)
2752 radeon_set_suspend(rinfo, 0);
2754 rinfo->asleep = 0;
2759 radeon_write_mode (rinfo, &rinfo->state, 1);
2761 radeonfb_engine_init (rinfo);
2770 rinfo->lock_blank = 0;
2771 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2783 if (rinfo->dynclk == 1)
2784 radeon_pm_enable_dynamic_mode(rinfo);
2785 else if (rinfo->dynclk == 0)
2786 radeon_pm_disable_dynamic_mode(rinfo);
2799 struct radeonfb_info *rinfo = data;
2801 rinfo->no_schedule = 1;
2802 pci_restore_state(rinfo->pdev);
2803 radeonfb_pci_resume(rinfo->pdev);
2804 rinfo->no_schedule = 0;
2810 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep)
2813 if (rinfo->family == CHIP_FAMILY_RS480)
2814 rinfo->dynclk = -1;
2816 rinfo->dynclk = dynclk;
2818 if (rinfo->dynclk == 1) {
2819 radeon_pm_enable_dynamic_mode(rinfo);
2821 } else if (rinfo->dynclk == 0) {
2822 radeon_pm_disable_dynamic_mode(rinfo);
2834 if (machine_is(powermac) && rinfo->of_node) {
2835 if (rinfo->is_mobility && rinfo->pdev->pm_cap &&
2836 rinfo->family <= CHIP_FAMILY_RV250)
2837 rinfo->pm_mode |= radeon_pm_d2;
2843 if (!strcmp(rinfo->of_node->name, "ATY,JasperParent") ||
2844 !strcmp(rinfo->of_node->name, "ATY,SnowyParent")) {
2845 rinfo->reinit_func = radeon_reinitialize_M10;
2846 rinfo->pm_mode |= radeon_pm_off;
2849 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
2850 rinfo->reinit_func = radeon_reinitialize_QW;
2851 rinfo->pm_mode |= radeon_pm_off;
2854 if (!strcmp(rinfo->of_node->name, "ATY,ViaParent")) {
2855 rinfo->reinit_func = radeon_reinitialize_M9P;
2856 rinfo->pm_mode |= radeon_pm_off;
2864 if (rinfo->pm_mode != radeon_pm_none) {
2865 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
2872 pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
2891 radeon_apply_workarounds(rinfo);
2896 rinfo->pm_mode |= radeon_pm_d2;
2900 void radeonfb_pm_exit(struct radeonfb_info *rinfo)
2903 if (rinfo->pm_mode != radeon_pm_none)