Lines Matching refs:reg
269 u32 reg;
283 reg = lcdc_read(LCD_RASTER_CTRL_REG);
284 if (!(reg & LCD_RASTER_ENABLE))
285 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
291 u32 reg;
294 reg = lcdc_read(LCD_RASTER_CTRL_REG);
295 if (reg & LCD_RASTER_ENABLE)
296 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
320 /* init reg to clear PLM (loading mode) fields */
377 u32 reg;
379 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
382 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
385 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
388 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
391 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
395 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
399 reg |= (fifo_th << 8);
401 lcdc_write(reg, LCD_DMA_CTRL_REG);
408 u32 reg;
411 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
412 reg |= LCD_AC_BIAS_FREQUENCY(period) |
414 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
420 u32 reg;
422 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
423 reg |= (((back_porch-1) & 0xff) << 24)
426 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
436 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff;
437 reg |= ((front_porch-1) & 0x300) >> 8;
438 reg |= ((back_porch-1) & 0x300) >> 4;
439 reg |= ((pulse_width-1) & 0x3c0) << 21;
440 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
447 u32 reg;
449 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
450 reg |= ((back_porch & 0xff) << 24)
453 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
459 u32 reg;
462 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
468 reg |= LCD_MONOCHROME_MODE;
470 reg |= LCD_MONO_8BIT_MODE;
473 reg |= LCD_TFT_MODE;
475 reg |= LCD_TFT_ALT_ENABLE;
482 reg |= LCD_STN_565_ENABLE;
491 reg |= LCD_V1_UNDERFLOW_INT_ENA;
498 lcdc_write(reg, LCD_RASTER_CTRL_REG);
500 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
502 reg |= LCD_SYNC_CTRL;
505 reg |= LCD_SYNC_EDGE;
507 reg &= ~LCD_SYNC_EDGE;
510 reg |= LCD_INVERT_LINE_CLOCK;
512 reg &= ~LCD_INVERT_LINE_CLOCK;
515 reg |= LCD_INVERT_FRAME_CLOCK;
517 reg &= ~LCD_INVERT_FRAME_CLOCK;
519 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
527 u32 reg;
548 reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
549 reg &= 0xfffffc00;
551 reg |= ((width >> 4) - 1) << 4;
554 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
556 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
560 reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
561 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
562 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
566 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
567 reg |= ((height - 1) & 0x400) << 16;
568 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
572 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
574 reg |= LCD_RASTER_ORDER;
585 reg |= LCD_V2_TFT_24BPP_MODE;
588 reg |= LCD_V2_TFT_24BPP_MODE;
589 reg |= LCD_V2_TFT_24BPP_UNPACK;
599 lcdc_write(reg, LCD_RASTER_CTRL_REG);