Lines Matching refs:reg
34 unsigned int reg;
36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
38 reg |= DSIM_FUNCRST;
40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
45 unsigned int reg;
47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
49 reg |= DSIM_SWRST;
51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
56 unsigned int reg;
58 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
60 reg |= INTSRC_SW_RST_RELEASE;
62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
73 unsigned int reg;
75 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK);
77 return reg;
83 unsigned int reg = 0;
86 reg |= mode;
88 reg &= ~mode;
90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK);
96 unsigned int reg;
98 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
100 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
102 reg |= cfg;
104 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
119 unsigned int reg;
121 reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL);
123 reg &= ~DSIM_MAIN_STAND_BY;
126 reg |= DSIM_MAIN_STAND_BY;
128 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
134 unsigned int reg;
137 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) &
139 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
141 reg &= ~((0x7ff << 16) | (0x7ff << 0));
142 reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);
144 reg |= DSIM_MAIN_STAND_BY;
145 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
151 unsigned int reg;
153 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) &
157 reg |= (DSIM_CMD_ALLOW_SHIFT(cmd_allow & 0xf) |
161 writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH);
167 unsigned int reg;
169 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) &
172 reg |= DSIM_MAIN_HFP_SHIFT(front) | DSIM_MAIN_HBP_SHIFT(back);
174 writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH);
180 unsigned int reg;
182 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) &
185 reg |= (DSIM_MAIN_VSA_SHIFT(vert & 0x3ff) |
188 writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC);
194 unsigned int reg;
196 reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) &
199 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
201 reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
202 reg |= (DSIM_SUB_VRESOL_SHIFT(vert & 0x7ff) |
204 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
206 reg |= DSIM_SUB_STANDY_SHIFT(1);
207 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
232 u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
237 reg |= (1 << 25);
239 reg &= ~(1 << 25);
246 reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << 26 |
250 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
256 unsigned int reg;
258 reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG);
261 reg |= DSIM_LANE_ENx(lane);
263 reg &= ~DSIM_LANE_ENx(lane);
265 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
283 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
286 reg |= (1 << 14);
287 reg &= ~(0x7 << 5);
288 reg |= (afc_code & 0x7) << 5;
290 reg &= ~(1 << 14);
292 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
298 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
301 reg |= DSIM_PLL_BYPASS_SHIFT(enable);
303 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
309 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
311 reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1);
313 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
319 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
322 reg |= DSIM_FREQ_BAND_SHIFT(freq_band & 0x1f);
324 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
331 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
334 reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 |
337 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
348 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
351 reg |= DSIM_PLL_EN_SHIFT(enable & 0x1);
353 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
359 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
362 reg |= (DSIM_BYTE_CLK_SRC_SHIFT(src));
364 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
370 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
373 reg |= DSIM_BYTE_CLKEN_SHIFT(enable);
375 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
381 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
384 reg |= DSIM_ESC_CLKEN_SHIFT(enable);
386 reg |= prs_val;
388 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
394 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
397 reg |= DSIM_LANE_ESC_CLKEN(lane_sel);
400 reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);
402 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
408 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
411 reg |= (DSIM_FORCE_STOP_STATE_SHIFT(enable & 0x1));
413 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
418 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
426 if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&
427 ((reg & DSIM_STOP_STATE_CLK) ||
428 (reg & DSIM_TX_READY_HS_CLK)))
437 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
440 reg |= (DSIM_STOP_STATE_CNT_SHIFT(cnt_val & 0x7ff));
442 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
448 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
451 reg |= (DSIM_BTA_TOUT_SHIFT(timeout));
453 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
459 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
462 reg |= (DSIM_LPDR_TOUT_SHIFT(timeout));
464 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
470 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
472 reg &= ~DSIM_CMD_LPDT_LP;
475 reg |= DSIM_CMD_LPDT_LP;
477 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
483 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
485 reg &= ~DSIM_TX_LPDT_LP;
488 reg |= DSIM_TX_LPDT_LP;
490 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
496 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
499 reg |= DSIM_TX_REQUEST_HSCLK_SHIFT(enable);
501 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
507 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
509 reg &= ~(0x3 << 0);
510 reg |= (swap_en & 0x3) << 0;
512 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
518 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
521 reg |= ((hs_zero & 0xf) << 28);
523 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
528 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
531 reg |= ((prep & 0x7) << 20);
533 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
544 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
546 reg |= src;
548 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
554 unsigned int reg = 0;
557 reg |= src;
559 reg &= ~src;
561 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
566 unsigned int reg;
568 reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
570 return reg & (1 << 31) ? 1 : 0;
581 unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0);
583 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
589 unsigned int reg = (data0 << 8) | (di << 0);
591 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
601 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
603 return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
608 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
610 writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +