Cross Reference: /drivers/video/fbdev/exynos/exynos_mipi_dsi

Lines Matching refs:reg_base
36 	reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
40 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
47 	reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
51 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
58 	reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
62 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
67 	return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) &
75 	reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK);
90 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK);
98 	reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
100 	writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
104 	writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
113 	writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
121 	reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL);
128 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
137 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) &
139 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
145 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
153 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) &
161 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH);
169 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) &
174 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH);
182 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) &
188 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC);
196 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) &
199 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
204 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
207 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
214 	unsigned int cfg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
226 	writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
232 	u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
250 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
258 	reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG);
265 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
277 	writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
283 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
292 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
298 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
303 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
309 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
313 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
319 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
324 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
331 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
337 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
343 	writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR);
348 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
353 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
359 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
364 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
370 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
375 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
381 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
388 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
394 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
402 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
408 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
413 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
418 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
437 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
442 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
448 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
453 	writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
459 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
464 	writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
470 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
477 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
483 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
490 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
496 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
501 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
507 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
512 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
518 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
523 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
528 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
533 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
538 	return readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
544 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
548 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
561 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
568 	reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
575 	return readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL) & ~(0x1f);
583 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
591 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
596 	return readl(dsim->reg_base + EXYNOS_DSIM_RXFIFO);
601 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
608 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
610 	writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +
617 	writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD);