Cross Reference: /drivers/video/fbdev/exynos/exynos_mipi_dsi

Lines Matching refs:writel
40 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
51 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
62 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
90 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK);
100 	writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
104 	writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
113 	writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
128 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
139 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
145 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
161 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH);
174 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH);
188 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC);
199 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
204 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
207 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
226 	writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
250 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
265 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
277 	writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
292 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
303 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
313 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
324 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
337 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
343 	writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR);
353 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
364 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
375 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
388 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
402 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
413 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
442 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
453 	writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
464 	writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
477 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
490 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
501 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
512 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
523 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
533 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
548 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
561 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
583 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
591 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
610 	writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +
617 	writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD);