Lines Matching refs:writel
90 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
97 writel(tcfg, par->dc_regs + DC_TIMING_CFG);
104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
108 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
114 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
135 writel(0, par->dc_regs + DC_FB_ST_OFFSET);
138 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);
139 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
166 writel(val, par->dc_regs + DC_H_TIMING_1);
168 writel(val, par->dc_regs + DC_H_TIMING_2);
170 writel(val, par->dc_regs + DC_H_TIMING_3);
171 writel(val, par->dc_regs + DC_FP_H_TIMING);
173 writel(val, par->dc_regs + DC_V_TIMING_1);
175 writel(val, par->dc_regs + DC_V_TIMING_2);
177 writel(val, par->dc_regs + DC_V_TIMING_3);
179 writel(val, par->dc_regs + DC_FP_V_TIMING);
182 writel(ocfg, par->dc_regs + DC_OUTPUT_CFG);
183 writel(tcfg, par->dc_regs + DC_TIMING_CFG);
185 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
190 writel(0, par->dc_regs + DC_UNLOCK);
207 writel(regno, par->dc_regs + DC_PAL_ADDRESS);
208 writel(val, par->dc_regs + DC_PAL_DATA);