Lines Matching defs:minfo
92 void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val)
99 int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg)
189 int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m)
196 struct matrox_hw_state * const hw = &minfo->hw;
246 divider = minfo->curr.final_bppShift;
276 wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
293 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
337 void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo)
340 struct matrox_hw_state * const hw = &minfo->hw;
529 static int parse_pins1(struct matrox_fb_info *minfo,
542 minfo->limits.pixel.vcomax = maxdac;
543 minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
546 minfo->features.pll.ref_freq = 14318;
547 minfo->values.reg.mctlwtst = 0x00030101;
551 static void default_pins1(struct matrox_fb_info *minfo)
554 minfo->limits.pixel.vcomax = 220000;
555 minfo->values.pll.system = 50000;
556 minfo->features.pll.ref_freq = 14318;
557 minfo->values.reg.mctlwtst = 0x00030101;
560 static int parse_pins2(struct matrox_fb_info *minfo,
563 minfo->limits.pixel.vcomax =
564 minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
565 minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
569 minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
570 minfo->features.pll.ref_freq = 14318;
574 static void default_pins2(struct matrox_fb_info *minfo)
577 minfo->limits.pixel.vcomax =
578 minfo->limits.system.vcomax = 230000;
579 minfo->values.reg.mctlwtst = 0x00030101;
580 minfo->values.pll.system = 50000;
581 minfo->features.pll.ref_freq = 14318;
584 static int parse_pins3(struct matrox_fb_info *minfo,
587 minfo->limits.pixel.vcomax =
588 minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
589 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
592 minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
596 minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
597 minfo->values.reg.opt2 = bd->pins[58] << 12;
598 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
602 static void default_pins3(struct matrox_fb_info *minfo)
605 minfo->limits.pixel.vcomax =
606 minfo->limits.system.vcomax = 230000;
607 minfo->values.reg.mctlwtst = 0x01250A21;
608 minfo->values.reg.memrdbk = 0x00000000;
609 minfo->values.reg.opt = 0x00000C00;
610 minfo->values.reg.opt2 = 0x00000000;
611 minfo->features.pll.ref_freq = 27000;
614 static int parse_pins4(struct matrox_fb_info *minfo,
617 minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
618 minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
619 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
620 minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
624 minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
627 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
628 minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
629 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
633 static void default_pins4(struct matrox_fb_info *minfo)
636 minfo->limits.pixel.vcomax =
637 minfo->limits.system.vcomax = 252000;
638 minfo->values.reg.mctlwtst = 0x04A450A1;
639 minfo->values.reg.memrdbk = 0x000000E7;
640 minfo->values.reg.opt = 0x10000400;
641 minfo->values.reg.opt3 = 0x0190A419;
642 minfo->values.pll.system = 200000;
643 minfo->features.pll.ref_freq = 27000;
646 static int parse_pins5(struct matrox_fb_info *minfo,
653 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
654 minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
655 minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
656 minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
657 minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
658 minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
659 minfo->values.pll.system =
660 minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
661 minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
662 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
663 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
664 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
665 minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
666 minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
667 minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
668 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
669 minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
670 minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
671 minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
673 minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
676 minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
677 wtst_xlat[minfo->values.reg.mctlwtst & 7];
679 minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
683 static void default_pins5(struct matrox_fb_info *minfo)
686 minfo->limits.pixel.vcomax =
687 minfo->limits.system.vcomax =
688 minfo->limits.video.vcomax = 600000;
689 minfo->limits.pixel.vcomin =
690 minfo->limits.system.vcomin =
691 minfo->limits.video.vcomin = 256000;
692 minfo->values.pll.system =
693 minfo->values.pll.video = 284000;
694 minfo->values.reg.opt = 0x404A1160;
695 minfo->values.reg.opt2 = 0x0000AC00;
696 minfo->values.reg.opt3 = 0x0090A409;
697 minfo->values.reg.mctlwtst_core =
698 minfo->values.reg.mctlwtst = 0x0C81462B;
699 minfo->values.reg.memmisc = 0x80000004;
700 minfo->values.reg.memrdbk = 0x01001103;
701 minfo->features.pll.ref_freq = 27000;
702 minfo->values.memory.ddr = 1;
703 minfo->values.memory.dll = 1;
704 minfo->values.memory.emrswen = 1;
705 minfo->values.reg.maccess = 0x00004000;
708 static int matroxfb_set_limits(struct matrox_fb_info *minfo,
714 switch (minfo->chip) {
715 case MGA_2064: default_pins1(minfo); break;
718 case MGA_1164: default_pins2(minfo); break;
720 case MGA_G200: default_pins3(minfo); break;
721 case MGA_G400: default_pins4(minfo); break;
723 case MGA_G550: default_pins5(minfo); break;
748 return parse_pins1(minfo, bd);
750 return parse_pins2(minfo, bd);
752 return parse_pins3(minfo, bd);
754 return parse_pins4(minfo, bd);
756 return parse_pins5(minfo, bd);
763 void matroxfb_read_pins(struct matrox_fb_info *minfo)
768 struct pci_dev *pdev = minfo->pcidev;
770 memset(&minfo->bios, 0, sizeof(minfo->bios));
774 pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
776 parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
780 if (!minfo->bios.bios_valid) {
794 parse_bios(b, &minfo->bios);
800 matroxfb_set_limits(minfo, &minfo->bios);
802 (minfo->values.reg.opt & 0x1C00) >> 10);