Lines Matching refs:reg
149 u16 reg;
252 return REG_GET(rfld.reg, rfld.high, rfld.low);
258 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
261 #define SR(reg) \
262 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
263 #define RR(reg) \
264 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
585 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
587 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
590 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
592 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
595 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
597 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
600 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
604 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
607 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
612 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
615 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
619 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);