Cross Reference: /drivers/video/fbdev/omap2/dss/hdmi

Lines Matching refs:pll
38 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
41 		hdmi_read_reg(pll->base, r))
54 void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy)
56 	struct hdmi_pll_info *pi = &pll->info;
107 static int hdmi_pll_config(struct hdmi_pll_data *pll)
110 	struct hdmi_pll_info *fmt = &pll->info;
113 	REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
115 	r = hdmi_read_reg(pll->base, PLLCTRL_CFG1);
118 	hdmi_write_reg(pll->base, PLLCTRL_CFG1, r);
120 	r = hdmi_read_reg(pll->base, PLLCTRL_CFG2);
132 	hdmi_write_reg(pll->base, PLLCTRL_CFG2, r);
134 	REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
136 	r = hdmi_read_reg(pll->base, PLLCTRL_CFG4);
139 	hdmi_write_reg(pll->base, PLLCTRL_CFG4, r);
142 	REG_FLD_MOD(pll->base, PLLCTRL_PLL_GO, 0x1, 0, 0);
145 	if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO,
152 	if (hdmi_wait_for_bit_change(pll->base,
156 			hdmi_read_reg(pll->base, PLLCTRL_CFG1));
158 			hdmi_read_reg(pll->base, PLLCTRL_CFG2));
160 			hdmi_read_reg(pll->base, PLLCTRL_CFG4));
169 static int hdmi_pll_reset(struct hdmi_pll_data *pll)
172 	REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, pll_feat->sys_reset, 3, 3);
175 	if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1)
184 int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
196 	r = hdmi_pll_reset(pll);
200 	r = hdmi_pll_config(pll);
207 void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
268 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll)
277 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
283 	pll->base = devm_ioremap_resource(&pdev->dev, res);
284 	if (IS_ERR(pll->base)) {
286 		return PTR_ERR(pll->base);