Cross Reference: /drivers/vme/bridges/vme

Lines Matching refs:bridge
57 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
59 	wake_up(&bridge->dma_queue);
64 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
72 			bridge->lm_callback[i](i);
81 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
83 	wake_up(&bridge->mbox_queue);
88 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
90 	wake_up(&bridge->iack_queue);
98 	struct ca91cx42_driver *bridge;
100 	bridge = ca91cx42_bridge->driver_priv;
102 	val = ioread32(bridge->base + DGCS);
115 	struct ca91cx42_driver *bridge;
117 	bridge = ca91cx42_bridge->driver_priv;
119 	val = ioread32(bridge->base + DGCS);
133 	struct ca91cx42_driver *bridge;
135 	bridge = ca91cx42_bridge->driver_priv;
140 			vec = ioread32(bridge->base +
156 	struct ca91cx42_driver *bridge;
160 	bridge = ca91cx42_bridge->driver_priv;
162 	enable = ioread32(bridge->base + LINT_EN);
163 	stat = ioread32(bridge->base + LINT_STAT);
172 		serviced |= ca91cx42_DMA_irqhandler(bridge);
175 		serviced |= ca91cx42_LM_irqhandler(bridge, stat);
177 		serviced |= ca91cx42_MB_irqhandler(bridge, stat);
179 		serviced |= ca91cx42_IACK_irqhandler(bridge);
191 	iowrite32(serviced, bridge->base + LINT_STAT);
200 	struct ca91cx42_driver *bridge;
202 	bridge = ca91cx42_bridge->driver_priv;
213 	iowrite32(0, bridge->base + VINT_EN);
216 	iowrite32(0, bridge->base + LINT_EN);
218 	iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
229 	iowrite32(0, bridge->base + LINT_MAP0);
230 	iowrite32(0, bridge->base + LINT_MAP1);
231 	iowrite32(0, bridge->base + LINT_MAP2);
238 	iowrite32(tmp, bridge->base + LINT_EN);
243 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
249 	iowrite32(0, bridge->base + VINT_EN);
252 	iowrite32(0, bridge->base + LINT_EN);
254 	iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
256 	ca91cx42_bridge = container_of((void *)bridge, struct vme_bridge,
261 static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level)
265 	tmp = ioread32(bridge->base + LINT_STAT);
282 	struct ca91cx42_driver *bridge;
284 	bridge = ca91cx42_bridge->driver_priv;
287 	tmp = ioread32(bridge->base + LINT_EN);
294 	iowrite32(tmp, bridge->base + LINT_EN);
308 	struct ca91cx42_driver *bridge;
310 	bridge = ca91cx42_bridge->driver_priv;
316 	mutex_lock(&bridge->vme_int);
318 	tmp = ioread32(bridge->base + VINT_EN);
321 	iowrite32(statid << 24, bridge->base + STATID);
325 	iowrite32(tmp, bridge->base + VINT_EN);
328 	wait_event_interruptible(bridge->iack_queue,
329 				 ca91cx42_iack_received(bridge, level));
332 	tmp = ioread32(bridge->base + VINT_EN);
334 	iowrite32(tmp, bridge->base + VINT_EN);
336 	mutex_unlock(&bridge->vme_int);
349 	struct ca91cx42_driver *bridge;
353 	bridge = ca91cx42_bridge->driver_priv;
412 	temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
414 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
417 	iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
418 	iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
419 	iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
437 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
442 	iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
453 	struct ca91cx42_driver *bridge;
455 	bridge = image->parent->driver_priv;
465 	ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
467 	*vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
468 	vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
469 	pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
608 	struct ca91cx42_driver *bridge;
612 	bridge = ca91cx42_bridge->driver_priv;
660 	temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
662 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
733 	iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
734 	iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
735 	iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
738 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
743 	iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
762 	struct ca91cx42_driver *bridge;
764 	bridge = image->parent->driver_priv;
768 	ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
770 	pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
771 	vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
772 	pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
875 	 * On the other hand, the bridge itself assures that the maximum data
980 	struct ca91cx42_driver *bridge;
983 	bridge = image->parent->driver_priv;
990 	mutex_lock(&bridge->vme_rmw);
1005 	iowrite32(0, bridge->base + SCYC_CTL);
1008 	iowrite32(mask, bridge->base + SCYC_EN);
1009 	iowrite32(compare, bridge->base + SCYC_CMP);
1010 	iowrite32(swap, bridge->base + SCYC_SWP);
1011 	iowrite32(pci_addr, bridge->base + SCYC_ADDR);
1014 	iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
1020 	iowrite32(0, bridge->base + SCYC_CTL);
1025 	mutex_unlock(&bridge->vme_rmw);
1179 	struct ca91cx42_driver *bridge;
1181 	bridge = ca91cx42_bridge->driver_priv;
1183 	tmp = ioread32(bridge->base + DGCS);
1199 	struct ca91cx42_driver *bridge;
1203 	bridge = ctrlr->parent->driver_priv;
1229 	iowrite32(0, bridge->base + DTBC);
1230 	iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1233 	val = ioread32(bridge->base + DGCS);
1242 	iowrite32(val, bridge->base + DGCS);
1246 	iowrite32(val, bridge->base + DGCS);
1248 	wait_event_interruptible(bridge->dma_queue,
1255 	val = ioread32(bridge->base + DGCS);
1261 		val = ioread32(bridge->base + DCTL);
1300 	struct ca91cx42_driver *bridge;
1303 	bridge = lm->parent->driver_priv;
1318 		if (bridge->lm_callback[i] != NULL) {
1352 	iowrite32(lm_base, bridge->base + LM_BS);
1353 	iowrite32(lm_ctl, bridge->base + LM_CTL);
1367 	struct ca91cx42_driver *bridge;
1369 	bridge = lm->parent->driver_priv;
1373 	*lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1374 	lm_ctl = ioread32(bridge->base + LM_CTL);
1410 	struct ca91cx42_driver *bridge;
1413 	bridge = lm->parent->driver_priv;
1419 	lm_ctl = ioread32(bridge->base + LM_CTL);
1427 	if (bridge->lm_callback[monitor] != NULL) {
1434 	bridge->lm_callback[monitor] = callback;
1437 	tmp = ioread32(bridge->base + LINT_EN);
1439 	iowrite32(tmp, bridge->base + LINT_EN);
1444 		iowrite32(lm_ctl, bridge->base + LM_CTL);
1458 	struct ca91cx42_driver *bridge;
1460 	bridge = lm->parent->driver_priv;
1465 	tmp = ioread32(bridge->base + LINT_EN);
1467 	iowrite32(tmp, bridge->base + LINT_EN);
1470 		 bridge->base + LINT_STAT);
1473 	bridge->lm_callback[monitor] = NULL;
1478 		tmp = ioread32(bridge->base + LM_CTL);
1480 		iowrite32(tmp, bridge->base + LM_CTL);
1491 	struct ca91cx42_driver *bridge;
1493 	bridge = ca91cx42_bridge->driver_priv;
1496 		slot = ioread32(bridge->base + VCSR_BS);
1540 	struct ca91cx42_driver *bridge;
1542 	bridge = ca91cx42_bridge->driver_priv;
1548 		iowrite32(geoid << 27, bridge->base + VCSR_BS);
1558 	bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1559 						     &bridge->crcsr_bus);
1560 	if (bridge->crcsr_kernel == NULL) {
1567 	iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1569 	tmp = ioread32(bridge->base + VCSR_CTL);
1571 	iowrite32(tmp, bridge->base + VCSR_CTL);
1580 	struct ca91cx42_driver *bridge;
1582 	bridge = ca91cx42_bridge->driver_priv;
1585 	tmp = ioread32(bridge->base + VCSR_CTL);
1587 	iowrite32(tmp, bridge->base + VCSR_CTL);
1590 	iowrite32(0, bridge->base + VCSR_TO);
1592 	pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1593 		bridge->crcsr_bus);
1608 	/* We want to support more than one of each bridge so we need to
1609 	 * dynamically allocate the bridge structure
1870 	struct ca91cx42_driver *bridge;
1873 	bridge = ca91cx42_bridge->driver_priv;
1877 	iowrite32(0, bridge->base + LINT_EN);
1880 	iowrite32(0x00800000, bridge->base + LSI0_CTL);
1881 	iowrite32(0x00800000, bridge->base + LSI1_CTL);
1882 	iowrite32(0x00800000, bridge->base + LSI2_CTL);
1883 	iowrite32(0x00800000, bridge->base + LSI3_CTL);
1884 	iowrite32(0x00800000, bridge->base + LSI4_CTL);
1885 	iowrite32(0x00800000, bridge->base + LSI5_CTL);
1886 	iowrite32(0x00800000, bridge->base + LSI6_CTL);
1887 	iowrite32(0x00800000, bridge->base + LSI7_CTL);
1888 	iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1889 	iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1890 	iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1891 	iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1892 	iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1893 	iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1894 	iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1895 	iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1930 	ca91cx42_irq_exit(bridge, pdev);
1932 	iounmap(bridge->base);
1946 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");