Cross Reference: /drivers/vme/bridges/vme

Lines Matching refs:bridge
77 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
83 		wake_up(&bridge->dma_queue[0]);
87 		wake_up(&bridge->dma_queue[1]);
97 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
105 			bridge->lm_callback[i](i);
123 	struct tsi148_driver *bridge;
125 	bridge = tsi148_bridge->driver_priv;
129 			val = ioread32be(bridge->base +	TSI148_GCSR_MBOX[i]);
144 	struct tsi148_driver *bridge;
146 	bridge = tsi148_bridge->driver_priv;
150 		ioread32be(bridge->base + TSI148_LCSR_EDPAU),
151 		ioread32be(bridge->base + TSI148_LCSR_EDPAL),
152 		ioread32be(bridge->base + TSI148_LCSR_EDPAT));
156 		ioread32be(bridge->base + TSI148_LCSR_EDPXA),
157 		ioread32be(bridge->base + TSI148_LCSR_EDPXS));
159 	iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
173 	struct tsi148_driver *bridge;
175 	bridge = tsi148_bridge->driver_priv;
177 	error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
178 	error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
179 	error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
208 	iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
216 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
218 	wake_up(&bridge->iack_queue);
230 	struct tsi148_driver *bridge;
232 	bridge = tsi148_bridge->driver_priv;
241 			vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
260 	struct tsi148_driver *bridge;
264 	bridge = tsi148_bridge->driver_priv;
267 	enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
268 	stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
279 		serviced |= tsi148_DMA_irqhandler(bridge, stat);
284 		serviced |= tsi148_LM_irqhandler(bridge, stat);
301 		serviced |= tsi148_IACK_irqhandler(bridge);
311 	iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
321 	struct tsi148_driver *bridge;
325 	bridge = tsi148_bridge->driver_priv;
376 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
377 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
385 	struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
388 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
389 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
392 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
401 static int tsi148_iack_received(struct tsi148_driver *bridge)
405 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
421 	struct tsi148_driver *bridge;
423 	bridge = tsi148_bridge->driver_priv;
427 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
429 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
431 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
433 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
440 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
442 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
444 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
446 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
458 	struct tsi148_driver *bridge;
460 	bridge = tsi148_bridge->driver_priv;
462 	mutex_lock(&bridge->vme_int);
465 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
470 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
474 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
477 	wait_event_interruptible(bridge->iack_queue,
478 		tsi148_iack_received(bridge));
480 	mutex_unlock(&bridge->vme_int);
566 	struct tsi148_driver *bridge;
569 	bridge = tsi148_bridge->driver_priv;
628 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
631 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
635 	iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
637 	iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
639 	iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
641 	iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
643 	iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
645 	iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
690 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
696 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
714 	struct tsi148_driver *bridge;
716 	bridge = image->parent->driver_priv;
721 	ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
724 	vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
726 	vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
728 	vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
730 	vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
732 	pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
734 	pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
910 	struct tsi148_driver *bridge;
916 	bridge = tsi148_bridge->driver_priv;
994 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
997 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1099 	iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1101 	iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1103 	iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1105 	iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1107 	iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1109 	iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1113 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1119 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1150 	struct tsi148_driver *bridge;
1152 	bridge = image->parent->driver_priv;
1156 	ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1159 	pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1161 	pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1163 	pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1165 	pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1167 	vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1169 	vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1285 	 * On the other hand, the bridge itself assures that the maximum data
1361 	struct tsi148_driver *bridge;
1365 	bridge = tsi148_bridge->driver_priv;
1428 	ioread16(bridge->flush_image->kern_base + 0x7F000);
1460 	struct tsi148_driver *bridge;
1462 	bridge = image->parent->driver_priv;
1468 	mutex_lock(&bridge->vme_rmw);
1473 	pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1475 	pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1482 	iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1483 	iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1484 	iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1485 	iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1486 	iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1489 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1491 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1497 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1499 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1503 	mutex_unlock(&bridge->vme_rmw);
1873 	struct tsi148_driver *bridge;
1875 	bridge = tsi148_bridge->driver_priv;
1877 	tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1900 	struct tsi148_driver *bridge;
1906 	bridge = tsi148_bridge->driver_priv;
1937 	iowrite32be(bus_addr_high, bridge->base +
1939 	iowrite32be(bus_addr_low, bridge->base +
1942 	dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1946 	iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1949 	wait_event_interruptible(bridge->dma_queue[channel],
1956 	val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
2010 	struct tsi148_driver *bridge;
2014 	bridge = tsi148_bridge->driver_priv;
2020 		if (bridge->lm_callback[i] != NULL) {
2059 	iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
2060 	iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
2061 	iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2075 	struct tsi148_driver *bridge;
2077 	bridge = lm->parent->driver_priv;
2081 	lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
2082 	lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
2083 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2127 	struct tsi148_driver *bridge;
2131 	bridge = tsi148_bridge->driver_priv;
2136 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2145 	if (bridge->lm_callback[monitor] != NULL) {
2152 	bridge->lm_callback[monitor] = callback;
2155 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2157 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
2159 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2161 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2166 		iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2180 	struct tsi148_driver *bridge;
2182 	bridge = lm->parent->driver_priv;
2187 	lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2189 	iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
2191 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2193 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2196 		 bridge->base + TSI148_LCSR_INTC);
2199 	bridge->lm_callback[monitor] = NULL;
2204 		tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2206 		iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
2220 	struct tsi148_driver *bridge;
2222 	bridge = tsi148_bridge->driver_priv;
2225 		slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2273 	struct tsi148_driver *bridge;
2275 	bridge = tsi148_bridge->driver_priv;
2278 	bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2279 						     &bridge->crcsr_bus);
2280 	if (bridge->crcsr_kernel == NULL) {
2286 	reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2288 	iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2289 	iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
2292 	cbar = ioread32be(bridge->base + TSI148_CBAR);
2300 		iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
2304 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2310 			bridge->base + TSI148_LCSR_CRAT);
2318 		retval = tsi148_master_set(bridge->flush_image, 1,
2334 	struct tsi148_driver *bridge;
2336 	bridge = tsi148_bridge->driver_priv;
2339 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2341 		bridge->base + TSI148_LCSR_CRAT);
2344 	iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2345 	iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
2347 	pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2348 		bridge->crcsr_bus);
2363 	/* If we want to support more than one of each bridge, we need to
2667 	struct tsi148_driver *bridge;
2670 	bridge = tsi148_bridge->driver_priv;
2679 		iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
2681 		iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
2688 	iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
2693 	iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
2698 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2699 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2700 	iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
2705 	if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2706 		iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
2711 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2712 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
2742 	iounmap(bridge->base);
2761 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");