Cross Reference: /kernel/irq/generic-chip.c

Lines Matching refs:mask
32  * Chip has separate enable/disable registers instead of a single mask
39 	u32 mask = d->mask;
42 	irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
43 	*ct->mask_cache &= ~mask;
48  * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
51  * Chip has a single mask register. Values of this register are cached
58 	u32 mask = d->mask;
61 	*ct->mask_cache |= mask;
62 	irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
68  * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
71  * Chip has a single mask register. Values of this register are cached
78 	u32 mask = d->mask;
81 	*ct->mask_cache &= ~mask;
82 	irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
91  * Chip has separate enable/disable registers instead of a single mask
98 	u32 mask = d->mask;
101 	irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
102 	*ct->mask_cache |= mask;
114 	u32 mask = d->mask;
117 	irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
130 	u32 mask = ~d->mask;
133 	irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
145 	u32 mask = d->mask;
148 	irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
149 	irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
161 	u32 mask = d->mask;
164 	irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
180 	u32 mask = d->mask;
182 	if (!(mask & gc->wake_enabled))
187 		gc->wake_active |= mask;
189 		gc->wake_active &= ~mask;
238 	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
244 			mskreg = ct[i].regs.mask;
390 		data->mask = 1 << idx;
444 				d->mask = 1 << (i - gc->irq_base);
500 		/* Remove handler first. That will mask the irq line */