Searched defs:REG (Results 1 - 14 of 14) sorted by relevance

/drivers/regulator/
H A Drn5t618-regulator.c31 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
49 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
50 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
51 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
53 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
54 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
55 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
56 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
57 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
59 REG(LDORTC
[all...]
/drivers/hwmon/
H A Dsmsc47b397.c54 #define REG 0x2e /* The register to read/write */ macro
59 outb(reg, REG);
65 outb(reg, REG);
77 outb(0x55, REG);
82 outb(0xAA, REG);
160 * REG: 1C/bit, two's complement
182 * REG: count of 90kHz pulses / revolution
H A Dsmsc47m1.c56 #define REG 0x2e /* The register to read/write */ macro
62 outb(reg, REG);
69 outb(reg, REG);
79 outb(0x55, REG);
85 outb(0xAA, REG);
H A Dit87.c77 #define REG 0x2e /* The register to read/write */ macro
90 outb(reg, REG);
96 outb(reg, REG);
103 outb(reg++, REG);
105 outb(reg, REG);
112 outb(DEV, REG);
119 * Try to reserve REG and REG + 1 for exclusive access.
121 if (!request_muxed_region(REG, 2, DRVNAME))
124 outb(0x87, REG);
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/drivers/gpu/drm/tilcdc/
H A Dtilcdc_drv.c430 #define REG(rev, save, reg) { #reg, rev, save, reg } macro
432 REG(1, false, LCDC_PID_REG),
433 REG(1, true, LCDC_CTRL_REG),
434 REG(1, false, LCDC_STAT_REG),
435 REG(1, true, LCDC_RASTER_CTRL_REG),
436 REG(1, true, LCDC_RASTER_TIMING_0_REG),
437 REG(1, true, LCDC_RASTER_TIMING_1_REG),
438 REG(1, true, LCDC_RASTER_TIMING_2_REG),
439 REG(1, true, LCDC_DMA_CTRL_REG),
440 REG(
452 #undef REG macro
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/drivers/watchdog/
H A Dit8712f_wdt.c61 #define REG 0x2e /* The register to read/write */ macro
99 outb(reg, REG);
105 outb(reg, REG);
112 outb(reg++, REG);
114 outb(reg, REG);
121 outb(LDN, REG);
128 * Try to reserve REG and REG + 1 for exclusive access.
130 if (!request_muxed_region(REG, 2, NAME))
133 outb(0x87, REG);
[all...]
H A Dit87_wdt.c64 #define REG 0x2e macro
176 * Try to reserve REG and REG + 1 for exclusive access.
178 if (!request_muxed_region(REG, 2, WATCHDOG_NAME))
181 outb(0x87, REG);
182 outb(0x01, REG);
183 outb(0x55, REG);
184 outb(0x55, REG);
190 outb(0x02, REG);
192 release_region(REG,
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/drivers/net/ethernet/apple/
H A Dmace.h13 #define REG(x) volatile unsigned char x; char x ## _pad[15] macro
16 REG(rcvfifo); /* receive FIFO */
17 REG(xmtfifo); /* transmit FIFO */
18 REG(xmtfc); /* transmit frame control */
19 REG(xmtfs); /* transmit frame status */
20 REG(xmtrc); /* transmit retry count */
21 REG(rcvfc); /* receive frame control */
22 REG(rcvfs); /* receive frame status (4 bytes) */
23 REG(fifofc); /* FIFO frame count */
24 REG(i
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/drivers/block/
H A Dswim.c44 #define REG(x) unsigned char x, x ## _pad[0x200 - 1]; macro
47 REG(write_data)
48 REG(write_mark)
49 REG(write_CRC)
50 REG(write_parameter)
51 REG(write_phase)
52 REG(write_setup)
53 REG(write_mode0)
54 REG(write_mode1)
56 REG(read_dat
[all...]
H A Dswim3.c59 #define REG(x) unsigned char x; char x ## _pad[15]; macro
66 REG(data);
67 REG(timer); /* counts down at 1MHz */
68 REG(error);
69 REG(mode);
70 REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
71 REG(setup);
72 REG(control); /* writing bits clears them */
73 REG(status); /* writing bits sets them in control */
74 REG(int
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/drivers/mmc/host/
H A Dvub300.c224 #define REG(c) (0x01FFFF & (c->arg>>9)) macro
1867 u32 reg = REG(cmd);
/drivers/gpu/drm/i2c/
H A Dtda998x_drv.c57 #define REG(page, addr) (((page) << 8) | (addr)) macro
65 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
66 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
73 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
74 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
77 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
78 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
79 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
83 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
85 #define REG_INT_FLAGS_0 REG(
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/drivers/scsi/sym53c8xx_2/
H A Dsym_defs.h385 #define REG(r) REGJ (nc_, r) macro
585 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
588 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
591 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
657 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
660 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
/drivers/scsi/
H A Dncr53c8xx.h911 #define REG(r) REGJ (nc_, r) macro
1101 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1104 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1107 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1173 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1176 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))

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