Searched defs:WBCIR_REG_SP3_ASCR (Results 1 - 1 of 1) sorted by relevance

/drivers/media/rc/
H A Dwinbond-cir.c91 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */ macro
137 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
139 /* RX disable bit for WBCIR_REG_SP3_ASCR */
141 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
377 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
459 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
467 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
508 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
984 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);

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