Searched defs:WRITE_REG (Results 1 - 7 of 7) sorted by relevance
/drivers/ata/ |
H A D | pata_opti.c | 39 WRITE_REG = 1, /* index of Write cycle timing register */ enumerator in enum:__anon50 143 opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG);
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H A D | pata_optidma.c | 38 WRITE_REG = 1, /* index of Write cycle timing register */ enumerator in enum:__anon51 169 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG); 172 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
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/drivers/ide/ |
H A D | opti621.c | 24 #define WRITE_REG 1 /* index of Write cycle timing register */ macro 117 write_reg(tim, WRITE_REG);
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/drivers/watchdog/ |
H A D | ar7_wdt.c | 58 #define WRITE_REG(x, v) writel((v), (void __iomem *)&(x)) macro 87 WRITE_REG(ar7_wdt->kick_lock, 0x5555); 89 WRITE_REG(ar7_wdt->kick_lock, 0xaaaa); 91 WRITE_REG(ar7_wdt->kick, value); 100 WRITE_REG(ar7_wdt->prescale_lock, 0x5a5a); 102 WRITE_REG(ar7_wdt->prescale_lock, 0xa5a5); 104 WRITE_REG(ar7_wdt->prescale, value); 113 WRITE_REG(ar7_wdt->change_lock, 0x6666); 115 WRITE_REG(ar7_wdt->change_lock, 0xbbbb); 117 WRITE_REG(ar7_wd [all...] |
/drivers/staging/rts5208/ |
H A D | ms.h | 52 #define WRITE_REG 0x0B macro
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/drivers/parisc/ |
H A D | sba_iommu.c | 136 #define WRITE_REG(value, addr) WRITE_REG64(value, addr) macro 139 #define WRITE_REG(value, addr) WRITE_REG32(value, addr) macro 665 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); 1306 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1319 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); 1340 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); 1346 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); 1352 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); 1468 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); 1469 WRITE_REG(io [all...] |
/drivers/net/ethernet/tehuti/ |
H A D | tehuti.h | 99 #define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg) macro
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