Searched defs:base_addr (Results 26 - 50 of 113) sorted by relevance

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/drivers/video/fbdev/
H A Dgrvga.c244 u32 base_addr; local
249 base_addr = fix->smem_start + (var->yoffset * fix->line_length);
250 base_addr &= ~3UL;
253 __raw_writel(base_addr,
H A Dpmag-aa-fb.c412 unsigned long base_addr = CKSEG1ADDR(get_tc_base_addr(slot)); local
420 ip->bt455 = (struct bt455_regs *) (base_addr + PMAG_AA_BT455_OFFSET);
421 ip->bt431 = (struct bt431_regs *) (base_addr + PMAG_AA_BT431_OFFSET);
422 ip->fb_start = base_addr + PMAG_AA_ONBOARD_FBMEM_OFFSET;
/drivers/watchdog/
H A Dsp5100_tco.c321 u32 index_reg, data_reg, base_addr; local
343 base_addr = SB800_PM_WATCHDOG_BASE;
348 base_addr = SP5100_PM_WATCHDOG_BASE;
361 outb(base_addr+3, index_reg);
363 outb(base_addr+2, index_reg);
365 outb(base_addr+1, index_reg);
367 outb(base_addr+0, index_reg);
H A Dsch311x_wdt.c464 unsigned short base_addr; local
486 base_addr = (sch311x_sio_inb(sio_config_port, 0x60) << 8) |
488 if (!base_addr) {
493 *addr = base_addr;
495 pr_info("Found an SMSC SCH311%d chip at 0x%04x\n", dev_id, base_addr);
/drivers/clocksource/
H A Dcadence_ttc_timer.c74 * @base_addr: Base address of timer
80 void __iomem *base_addr; member in struct:ttc_timer
121 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
123 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
125 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
133 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
150 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
166 return (cycle_t)readl_relaxed(timer->base_addr +
214 ctrl_reg = readl_relaxed(timer->base_addr +
218 timer->base_addr
[all...]
/drivers/net/appletalk/
H A Dcops.c203 release_region(dev->base_addr, COPS_IO_EXTENT);
208 * If dev->base_addr == 0, probe all likely locations.
209 * If dev->base_addr in [1..0x1ff], always return failure.
216 int base_addr; local
227 base_addr = dev->base_addr;
229 base_addr = dev->base_addr = io;
232 if (base_addr > 0x1ff) { /* Check a single specified location. */
233 err = cops_probe1(dev, base_addr);
[all...]
/drivers/net/ethernet/8390/
H A Dsmc-ultra.c123 #define ULTRA_NIC_OFFSET 16 /* NIC register offset from the base_addr. */
143 int base_addr = dev->base_addr; local
146 if (base_addr > 0x1ff) /* Check a single specified location. */
147 return ultra_probe1(dev, base_addr);
148 else if (base_addr != 0) /* Don't probe at all. */
279 dev->base_addr = ioaddr+ULTRA_NIC_OFFSET;
361 dev->base_addr = pnp_port_start(idev, 0);
366 dev->base_addr, dev->irq);
367 if (ultra_probe1(dev, dev->base_addr) !
[all...]
H A Dwd.c75 #define WD_NIC_OFFSET 16 /* Offset to the 8390 from the base_addr. */
91 int base_addr = dev->base_addr; local
96 if (base_addr > 0x1ff) { /* Check a user specified location. */
97 r = request_region(base_addr, WD_IO_EXTENT, "wd-probe");
100 i = wd_probe1(dev, base_addr);
102 release_region(base_addr, WD_IO_EXTENT);
107 else if (base_addr != 0) /* Don't probe at all. */
277 dev->base_addr = ioaddr+WD_NIC_OFFSET;
374 int ioaddr = dev->base_addr
[all...]
H A Dne.c156 #define NE_BASE (dev->base_addr)
213 unsigned long base_addr = dev->base_addr; local
219 if (base_addr > 0x1ff) { /* Check a single specified location. */
220 int ret = ne_probe1(dev, base_addr);
223 "i/o = %#lx\n", base_addr);
226 else if (base_addr != 0) /* Don't probe at all. */
235 for (base_addr = 0; netcard_portlist[base_addr] != 0; base_addr
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/drivers/net/ethernet/amd/
H A Dam79c961a.c59 static inline unsigned short read_rreg(u_long base_addr, u_int reg) argument
79 static inline unsigned short read_ireg(u_long base_addr, u_int reg) argument
247 write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0_STOP);
250 write_ireg (dev->base_addr, 5, 0x00a0); /* Receive address LED */
251 write_ireg (dev->base_addr, 6, 0x0081); /* Collision LED */
252 write_ireg (dev->base_addr, 7, 0x0090); /* XMIT LED */
253 write_ireg (dev->base_addr, 2, 0x0000); /* MODE register selects media */
256 write_rreg (dev->base_addr, i, multi_hash[i - LADRL]);
259 write_rreg (dev->base_addr, i, p[0] | (p[1] << 8));
261 write_rreg (dev->base_addr, MOD
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H A Dariadne.c242 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr;
394 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr;
499 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr;
524 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr;
535 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr;
547 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr;
623 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr;
645 volatile struct Am79C960 *lance = (struct Am79C960 *)dev->base_addr;
690 release_mem_region(ZTWO_PADDR(dev->base_addr), sizeof(struct Am79C960));
717 unsigned long base_addr local
[all...]
H A Da2065.c679 unsigned long base_addr = board + A2065_LANCE; local
685 r1 = request_mem_region(base_addr, sizeof(struct lance_regs),
691 release_mem_region(base_addr, sizeof(struct lance_regs));
697 release_mem_region(base_addr, sizeof(struct lance_regs));
719 dev->base_addr = (unsigned long)ZTWO_VADDR(base_addr);
723 priv->ll = (volatile struct lance_regs *)dev->base_addr;
745 release_mem_region(base_addr, sizeof(struct lance_regs));
764 release_mem_region(ZTWO_PADDR(dev->base_addr),
/drivers/net/ethernet/chelsio/cxgb3/
H A Dcxgb3_ctl_defs.h159 unsigned long long base_addr; member in struct:rdma_cq_setup
170 unsigned long long base_addr; member in struct:rdma_ctrlqp_setup
/drivers/net/ethernet/realtek/
H A Datp.c213 If dev->base_addr == 0, probe all likely locations.
214 If dev->base_addr == 1, always return failure.
215 If dev->base_addr == 2, allocate space for the device and return success
223 int base_addr = io[0]; local
225 if (base_addr > 0x1ff) /* Check a single specified location. */
226 return atp_probe1(base_addr);
227 else if (base_addr == 1) /* Don't probe at all. */
323 dev->base_addr = ioaddr;
335 dev->name, dev->base_addr, dev->irq, dev->dev_addr);
370 long ioaddr = dev->base_addr;
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/drivers/platform/x86/
H A Dintel_mid_thermal.c251 * @base_addr: index of free msic ADC channel
257 static int set_up_therm_channel(u16 base_addr) argument
262 ret = intel_msic_reg_write(base_addr, SKIN_SENSOR0_CODE);
266 ret = intel_msic_reg_write(base_addr + 1, SKIN_SENSOR1_CODE);
270 ret = intel_msic_reg_write(base_addr + 2, SYS_SENSOR_CODE);
276 ret = intel_msic_reg_write(base_addr + 3,
352 u16 base_addr; local
375 base_addr = ADC_CHNL_START_ADDR + channel_index;
379 ret = reset_stopbit(base_addr);
384 base_addr
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/drivers/spi/
H A Dspi-sun4i.c78 void __iomem *base_addr; member in struct:sun4i_spi
91 return readl(sspi->base_addr + reg);
96 writel(value, sspi->base_addr + reg);
113 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
128 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
369 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
370 if (IS_ERR(sspi->base_addr)) {
371 ret = PTR_ERR(sspi->base_addr);
/drivers/staging/media/davinci_vpfe/
H A Ddm365_ipipe.h123 void *__iomem base_addr; member in struct:vpfe_ipipe_device
/drivers/crypto/qat/qat_common/
H A Dadf_accel_devices.h79 resource_size_t base_addr; member in struct:adf_bar
/drivers/dma/sh/
H A Dsudmac.c43 u32 base_addr; member in struct:sudmac_regs
106 sudmac_writel(sc, hw->base_addr, SUDMAC_CH0BA + sc->offset);
189 sd->hw.base_addr = dst;
191 sd->hw.base_addr = src;
235 return sd->hw.base_addr + sd->hw.base_byte_count == current_addr;
/drivers/gpio/
H A Dgpio-zynq.c89 * @base_addr: base address of the GPIO device
95 void __iomem *base_addr; member in struct:zynq_gpio
166 data = readl_relaxed(gpio->base_addr +
206 writel_relaxed(state, gpio->base_addr + reg_offset);
232 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
234 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
261 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
263 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
266 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
268 writel_relaxed(reg, gpio->base_addr
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/drivers/media/platform/davinci/
H A Ddm355_ccdc.c62 void __iomem *base_addr; member in struct:ccdc_oper_config
129 return __raw_readl(ccdc_cfg.base_addr + offset);
134 __raw_writel(val, ccdc_cfg.base_addr + offset);
989 ccdc_cfg.base_addr = ioremap_nocache(res->start, resource_size(res));
990 if (!ccdc_cfg.base_addr) {
1010 iounmap(ccdc_cfg.base_addr);
1022 iounmap(ccdc_cfg.base_addr);
H A Ddm644x_ccdc.c63 void __iomem *base_addr; member in struct:ccdc_oper_config
106 return __raw_readl(ccdc_cfg.base_addr + offset);
111 __raw_writel(val, ccdc_cfg.base_addr + offset);
978 ccdc_cfg.base_addr = ioremap_nocache(res->start, resource_size(res));
979 if (!ccdc_cfg.base_addr) {
998 iounmap(ccdc_cfg.base_addr);
H A Disif.c91 void __iomem *base_addr; member in struct:isif_oper_config
153 return __raw_readl(isif_cfg.base_addr + offset);
158 __raw_writel(val, isif_cfg.base_addr + offset);
1080 isif_cfg.base_addr = addr;
1102 if (isif_cfg.base_addr)
1103 iounmap(isif_cfg.base_addr);
1121 iounmap(isif_cfg.base_addr);
/drivers/misc/
H A Dhpilo.c209 static void fifo_setup(void *base_addr, int nr_entry) argument
211 struct fifo *fifo_q = base_addr;
/drivers/misc/mei/
H A Dhw-txe.c33 * @base_addr: registers base address
38 static inline u32 mei_txe_reg_read(void __iomem *base_addr, argument
41 return ioread32(base_addr + offset);
47 * @base_addr: registers base address
51 static inline void mei_txe_reg_write(void __iomem *base_addr, argument
54 iowrite32(value, base_addr + offset);

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