Searched defs:bpp (Results 1 - 25 of 159) sorted by relevance

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/drivers/gpu/drm/rcar-du/
H A Drcar_du_kms.h26 unsigned int bpp; member in struct:rcar_du_format_info
H A Drcar_du_kms.c36 .bpp = 16,
42 .bpp = 16,
48 .bpp = 16,
54 .bpp = 32,
60 .bpp = 32,
66 .bpp = 16,
72 .bpp = 16,
78 .bpp = 12,
84 .bpp = 12,
91 .bpp
142 unsigned int bpp; local
[all...]
/drivers/gpu/drm/shmobile/
H A Dshmob_drm_kms.h24 unsigned int bpp; member in struct:shmob_drm_format_info
H A Dshmob_drm_plane.c50 unsigned int bpp; local
52 bpp = splane->format->yuv ? 8 : splane->format->bpp;
55 + y * fb->pitches[0] + x * bpp / 8;
58 bpp = splane->format->bpp - 8;
61 + y / (bpp == 4 ? 2 : 1) * fb->pitches[1]
62 + x * (bpp == 16 ? 2 : 1);
/drivers/video/fbdev/via/
H A Dioctl.c81 int viafb_ioctl_hotplug(int hres, int vres, int bpp) argument
H A Dvia_utility.c132 void viafb_set_gamma_table(int bpp, unsigned int *gamma_table) argument
144 /* 8 bpp mode can't adjust gamma */
145 if (bpp == 8)
236 void viafb_get_gamma_support_state(int bpp, unsigned int *support_state) argument
238 if (bpp == 8)
/drivers/video/fbdev/
H A Dc2p_iplan2.c48 static inline void store_iplan2(void *dst, u32 bpp, u32 d[4]) argument
52 for (i = 0; i < bpp/2; i++, dst += 4)
61 static inline void store_iplan2_masked(void *dst, u32 bpp, u32 d[4], u32 mask) argument
65 for (i = 0; i < bpp/2; i++, dst += 4)
82 * @bpp: Bits per pixel of the planar frame buffer (2, 4, or 8)
86 u32 height, u32 dst_nextline, u32 src_nextline, u32 bpp)
96 dst += dy*dst_nextline+(dx & ~15)*bpp;
113 store_iplan2_masked(p, bpp, d.words, first);
114 p += bpp*2;
125 store_iplan2_masked(p, bpp,
85 c2p_iplan2(void *dst, const void *src, u32 dx, u32 dy, u32 width, u32 height, u32 dst_nextline, u32 src_nextline, u32 bpp) argument
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H A Dc2p_planar.c48 static inline void store_planar(void *dst, u32 dst_inc, u32 bpp, u32 d[8]) argument
52 for (i = 0; i < bpp; i++, dst += dst_inc)
61 static inline void store_planar_masked(void *dst, u32 dst_inc, u32 bpp, argument
66 for (i = 0; i < bpp; i++, dst += dst_inc)
83 * @bpp: Bits per pixel of the planar frame buffer (1-8)
88 u32 src_nextline, u32 bpp)
113 store_planar_masked(p, dst_nextplane, bpp, d.words,
126 store_planar_masked(p, dst_nextplane, bpp,
136 store_planar(p, dst_nextplane, bpp, d.words);
146 store_planar_masked(p, dst_nextplane, bpp,
86 c2p_planar(void *dst, const void *src, u32 dx, u32 dy, u32 width, u32 height, u32 dst_nextline, u32 dst_nextplane, u32 src_nextline, u32 bpp) argument
[all...]
H A D68328fb.c114 static u_long get_line_length(int xres_virtual, int bpp) argument
118 length = xres_virtual * bpp;
/drivers/video/fbdev/core/
H A Dcfbfillrect.c283 u32 bpp = p->var.bits_per_pixel; local
296 pat = pixel_to_pat(bpp, fg);
300 dst_idx += rect->dy*p->fix.line_length*8+rect->dx*bpp;
301 /* FIXME For now we support 1-32 bpp only */
302 left = bits % bpp;
327 fill_op32(p, dst, dst_idx, pat, width*bpp, bits,
338 left = bpp - right;
340 right = bpp - left;
357 r = dst_idx % bpp;
359 pat2 = le_long_to_cpu(rolx(cpu_to_le_long(pat), r, bpp));
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H A Dsysfillrect.c248 u32 bpp = p->var.bits_per_pixel; local
261 pat = pixel_to_pat( bpp, fg);
265 dst_idx += rect->dy*p->fix.line_length*8+rect->dx*bpp;
266 /* FIXME For now we support 1-32 bpp only */
267 left = bits % bpp;
291 fill_op32(p, dst, dst_idx, pat, width*bpp, bits);
301 left = bpp - right;
303 right = bpp - left;
321 r = dst_idx % bpp;
323 pat2 = le_long_to_cpu(rolx(cpu_to_le_long(pat), r, bpp));
[all...]
H A Dfb_draw.h25 pixel_to_pat( u32 bpp, u32 pixel) argument
27 switch (bpp) {
45 WARN(1, "pixel_to_pat(): unsupported pixelformat %d\n", bpp);
51 pixel_to_pat( u32 bpp, u32 pixel) argument
53 switch (bpp) {
71 WARN(1, "pixel_to_pat(): unsupported pixelformat %d\n", bpp);
147 unsigned bpp = info->var.bits_per_pixel; local
149 if ((bpp < 8) && (info->var.nonstd & FB_NONSTD_REV_PIX_IN_B)) {
152 * works only for 1, 2 and 4 bpp
154 bswapmask = 7 - bpp
[all...]
/drivers/gpu/drm/armada/
H A Darmada_drm.h32 static inline uint32_t armada_pitch(uint32_t width, uint32_t bpp) argument
34 uint32_t pitch = bpp != 4 ? width * ((bpp + 7) / 8) : width / 2;
/drivers/gpu/drm/nouveau/
H A Dnouveau_display.h31 int crtc, bpp, pitch, x, y; member in struct:nouveau_page_flip_state
/drivers/video/fbdev/geode/
H A Ddisplay_gx.c55 int gx_line_delta(int xres, int bpp) argument
58 return (xres * (bpp >> 3) + 7) & ~0x7;
/drivers/gpu/drm/ast/
H A Dast_fb.c53 int bpp = (afbdev->afb.base.bits_per_pixel + 7)/8; local
114 src_offset = dst_offset = i * afbdev->afb.base.pitches[0] + (x * bpp);
115 memcpy_toio(bo->kmap.virtual + src_offset, afbdev->sysram + src_offset, (x2 - x + 1) * bpp);
170 u32 bpp, depth; local
175 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
/drivers/gpu/drm/cirrus/
H A Dcirrus_fbdev.c27 int bpp = (afbdev->gfb.base.bits_per_pixel + 7)/8; local
87 src_offset = dst_offset = i * afbdev->gfb.base.pitches[0] + (x * bpp);
88 memcpy_toio(bo->kmap.virtual + src_offset, afbdev->sysram + src_offset, width * bpp);
142 u32 bpp, depth; local
147 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
149 if (bpp > 24)
H A Dcirrus_main.c55 u32 bpp, depth; local
57 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
58 /* cirrus can't handle > 24bpp framebuffers at all */
59 if (bpp > 24)
241 args->pitch = args->width * ((args->bpp + 7) / 8);
/drivers/gpu/drm/i915/
H A Dintel_dp_mst.c39 int bpp; local
48 bpp = 24;
72 mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
77 intel_link_compute_m_n(bpp, lane_count,
/drivers/gpu/drm/mgag200/
H A Dmgag200_fb.c29 int bpp = (mfbdev->mfb.base.bits_per_pixel + 7)/8; local
90 src_offset = dst_offset = i * mfbdev->mfb.base.pitches[0] + (x * bpp);
91 memcpy_toio(bo->kmap.virtual + src_offset, mfbdev->sysram + src_offset, (x2 - x + 1) * bpp);
288 /* prefer 16bpp on low end gpus with limited VRAM */
/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4_lcdc_encoder.c113 int bpp, nchan, swap; local
118 bpp = 3 * connector->display_info.bpc;
120 if (!bpp)
121 bpp = 18;
127 switch (bpp) {
226 dev_err(dev->dev, "unknown bpp: %d\n", bpp);
413 /* TODO: hard-coded for 18bpp: */
/drivers/gpu/drm/msm/
H A Dmsm_drv.h239 static inline int align_pitch(int width, int bpp) argument
241 int bytespp = (bpp + 7) / 8;
/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.h57 extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
390 nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp) argument
395 if (bpp == 15)
396 bpp = 16;
397 if (bpp == 24)
398 bpp = 8;
402 mask = 128 / bpp - 1;
404 mask = 512 / bpp - 1;
/drivers/gpu/drm/omapdrm/
H A Domap_drv.h259 static inline int align_pitch(int pitch, int width, int bpp) argument
261 int bytespp = (bpp + 7) / 8;
/drivers/gpu/drm/radeon/
H A Dradeon_fb.c66 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) argument
72 switch (bpp / 8) {
116 u32 bpp, depth; local
118 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
121 mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
122 fb_tiled) * ((bpp + 1) / 8);
142 switch (bpp) {
207 /* avivo can't scanout real 24bpp */
346 /* select 8 bpp console on RN50 or 16MB cards */

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