Searched defs:byteout (Results 1 - 20 of 20) sorted by relevance

/drivers/isdn/hisax/
H A Dnetjet.h15 #define byteout(addr, val) outb(val, addr) macro
H A Dasuscom.c25 #define byteout(addr, val) outb(val, addr) macro
48 byteout(ale, off);
56 byteout(ale, off);
64 byteout(ale, off);
65 byteout(adr, data);
71 byteout(ale, off);
255 byteout(cs->hw.asus.adr, ASUS_RESET); /* Reset On */
260 byteout(cs->hw.asus.adr, 0); /* Reset Off */
H A Davm_a1.c25 #define byteout(addr, val) outb(val, addr) macro
37 byteout(adr + off, data);
112 byteout(cs->hw.avm.cfg_reg, 0x1E);
169 byteout(cs->hw.avm.cfg_reg, 0x16);
170 byteout(cs->hw.avm.cfg_reg, 0x1E);
251 byteout(cs->hw.avm.cfg_reg, 0x0);
253 byteout(cs->hw.avm.cfg_reg, 0x1);
255 byteout(cs->hw.avm.cfg_reg, 0x0);
260 byteout(cs->hw.avm.cfg_reg + 1, val);
262 byteout(c
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H A Davm_a1p.c56 #define byteout(addr, val) outb(val, addr) macro
67 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_REG_OFFSET + offset);
76 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_REG_OFFSET + offset);
77 byteout(cs->hw.avm.cfg_reg + DATAREG_OFFSET, value);
83 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_FIFO_OFFSET);
90 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_FIFO_OFFSET);
100 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET,
110 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET,
112 byteout(cs->hw.avm.cfg_reg + DATAREG_OFFSET, value);
118 byteout(c
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H A Disurf.c22 #define byteout(addr, val) outb(val, addr) macro
136 byteout(cs->hw.isurf.reset, chips); /* Reset On */
138 byteout(cs->hw.isurf.reset, ISURF_ISAR_EA); /* Reset Off */
H A Dix1_micro.c29 #define byteout(addr, val) outb(val, addr) macro
46 byteout(ale, off);
54 byteout(ale, off);
62 byteout(ale, off);
63 byteout(adr, data);
69 byteout(ale, off);
179 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 1);
182 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 0);
H A Dmic.c21 #define byteout(addr, val) outb(val, addr) macro
36 byteout(ale, off);
44 byteout(ale, off);
52 byteout(ale, off);
53 byteout(adr, data);
59 byteout(ale, off);
H A Dniccy.c26 #define byteout(addr, val) outb(val, addr) macro
50 byteout(ale, off);
58 byteout(ale, off);
65 byteout(ale, off);
66 byteout(adr, data);
72 byteout(ale, off);
H A Dsaphir.c23 #define byteout(addr, val) outb(val, addr) macro
38 byteout(ale, off);
46 byteout(ale, off);
54 byteout(ale, off);
55 byteout(adr, data);
61 byteout(ale, off);
176 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, 0xff);
207 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val);
208 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 1);
210 byteout(c
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H A Dsportster.c23 #define byteout(addr, val) outb(val, addr) macro
62 byteout(calc_off(cs->hw.spt.isac, offset), value);
86 byteout(calc_off(cs->hw.spt.hscx[hscx], offset), value);
94 #define WRITEHSCX(cs, nr, reg, data) byteout(calc_off(cs->hw.spt.hscx[nr], reg), data)
139 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, 0);
150 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
153 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
176 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq);
H A Dteleint.c21 #define byteout(addr, val) outb(val, addr) macro
30 byteout(ale, off);
49 byteout(ale, off);
69 byteout(ale, off);
77 byteout(adr, data);
87 byteout(ale, off);
96 byteout(adr, data[i]);
137 byteout(cs->hw.hfc.addr | 1, reg);
149 byteout(cs->hw.hfc.addr | 1, reg);
152 byteout(c
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H A Dteles0.c27 #define byteout(addr, val) outb(val, addr) macro
229 byteout(cs->hw.teles0.cfg_reg + 4, cfval);
231 byteout(cs->hw.teles0.cfg_reg + 4, cfval | 1);
H A Dteles3.c25 #define byteout(addr, val) outb(val, addr) macro
37 byteout(adr + off, data);
209 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg);
211 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg | 1);
214 byteout(cs->hw.teles3.cfg_reg, 0xff);
216 byteout(cs->hw.teles3.cfg_reg, 0x00);
220 byteout(cs->hw.teles3.isac + 0x3c, 0);
222 byteout(cs->hw.teles3.isac + 0x3c, 1);
H A Dgazel.c41 #define byteout(addr, val) outb(val, addr) macro
53 byteout(adr + off, data);
74 byteout(adr, off);
82 byteout(adr, off);
83 byteout(adr + 4, data);
90 byteout(adr, off);
97 byteout(adr, off);
H A Dhfc_2bds0.c25 #define byteout(addr, val) outb(val, addr) macro
42 byteout(cs->hw.hfcD.addr | 1, reg);
59 byteout(cs->hw.hfcD.addr | 1, reg);
62 byteout(cs->hw.hfcD.addr, value);
H A Dhfc_sx.c55 #define byteout(addr, val) outb(val, addr) macro
64 byteout(cs->hw.hfcsx.base + 1, regnum);
65 byteout(cs->hw.hfcsx.base, val);
73 byteout(cs->hw.hfcsx.base + 1, regnum);
88 byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL);
89 byteout(cs->hw.hfcsx.base, fifo);
92 byteout(cs->hw.hfcsx.base, fifo);
104 byteout(cs->hw.hfcsx.base + 1, HFCSX_CIRM);
105 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */
1457 byteout(c
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H A Ddiva.c30 #define byteout(addr, val) outb(val, addr) macro
86 byteout(ale, off);
94 byteout(ale, off);
102 byteout(ale, off);
103 byteout(adr, data);
109 byteout(ale, off);
725 byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */
780 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
783 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
789 byteout(c
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H A Delsa.c44 #define byteout(addr, val) outb(val, addr) macro
146 byteout(ale, off);
154 byteout(ale, off);
162 byteout(ale, off);
163 byteout(adr, data);
169 byteout(ale, off);
242 byteout(cs->hw.elsa.ale, off);
250 byteout(cs->hw.elsa.ale, off);
251 byteout(cs->hw.elsa.itac, data);
339 byteout(c
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H A Dsedlbauer.c83 #define byteout(addr, val) outb(val, addr) macro
124 byteout(ale, off);
132 byteout(ale, off);
140 byteout(ale, off);
141 byteout(adr, data);
147 byteout(ale, off);
227 byteout(cs->hw.sedl.adr, offset);
238 byteout(cs->hw.sedl.adr, offset);
239 byteout(cs->hw.sedl.hscx, value);
427 byteout(c
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/drivers/isdn/hysdn/
H A Dboardergo.c28 #define byteout(addr, val) outb(val, addr) macro
140 byteout(card->iobase + PCI9050_INTR_REG, val);
142 byteout(card->iobase + PCI9050_USER_IO, PCI9050_E1_RESET); /* reset E1 processor */
241 byteout(card->iobase + PCI9050_USER_IO, PCI9050_E1_RUN); /* start E1 processor */
356 byteout(card->iobase + PCI9050_INTR_REG,

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