Searched defs:clk (Results 1 - 25 of 198) sorted by relevance

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/arch/mips/loongson1/common/
H A Dclock.c10 #include <linux/clk.h>
17 struct clk *clk; local
23 clk = clk_get(NULL, "cpu");
24 if (IS_ERR(clk))
25 panic("unable to get cpu clock, err=%ld", PTR_ERR(clk));
27 mips_hpt_frequency = clk_get_rate(clk) / 2;
/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c14 #include <linux/clk.h>
25 * @clk: struct clk * of the DPLL to operate on
32 static void _allow_idle(struct clk_hw_omap *clk) argument
34 if (!clk || !clk->dpll_data)
42 * @clk: struct clk * of the DPLL to operate on
46 static void _deny_idle(struct clk_hw_omap *clk) argument
48 if (!clk || !cl
[all...]
H A Dclock2430.c21 #include <linux/clk.h>
33 * @clk: struct clk * being enabled
43 static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, argument
49 *idlest_bit = clk->enable_bit;
H A Dclkt_iclk.c14 #include <linux/clk-provider.h>
26 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) argument
32 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
34 v = omap2_clk_readl(clk, r);
35 v |= (1 << clk->enable_bit);
36 omap2_clk_writel(v, clk, r);
40 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) argument
46 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
48 v = omap2_clk_readl(clk, r);
49 v &= ~(1 << clk
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H A Dclock36xx.c22 #include <linux/clk.h>
23 #include <linux/clk-provider.h>
33 * @clk: DPLL output struct clk
41 int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) argument
46 struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk);
50 ret = omap2_dflt_clk_enable(clk);
52 parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
H A Dclock34xx.c21 #include <linux/clk.h>
31 * @clk: struct clk * being enabled
40 static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, argument
47 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
66 * @clk: struct clk * being enabled
78 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, argument
85 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
106 * @clk
115 omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) argument
[all...]
/arch/arm/mach-msm/
H A Dclock.c17 #include <linux/clk-provider.h>
22 int clk_reset(struct clk *clk, enum clk_reset_action action) argument
24 struct clk_hw *hw = __clk_get_hw(clk);
/arch/arm/mach-w90x900/
H A Dclock.h15 void nuc900_clk_enable(struct clk *clk, int enable);
16 void nuc900_subclk_enable(struct clk *clk, int enable);
18 struct clk { struct
21 void (*enable)(struct clk *, int enable);
25 struct clk clk_##_name = { \
31 struct clk clk_##_name = { \
39 .clk = _clk, \
/arch/c6x/include/asm/
H A Dclkdev.h6 struct clk;
8 static inline int __clk_get(struct clk *clk) argument
13 static inline void __clk_put(struct clk *clk) argument
/arch/microblaze/kernel/cpu/
H A Dcpuinfo.c11 #include <linux/clk.h>
109 struct clk *clk; local
111 clk = of_clk_get(cpu, 0);
112 if (IS_ERR(clk)) {
117 cpuinfo.cpu_clock_freq = clk_get_rate(clk);
/arch/mips/lasat/
H A Dat93c.h14 u32 clk; member in struct:at93c_defs
/arch/powerpc/sysdev/qe_lib/
H A Dusb.c23 int qe_usb_clock_set(enum qe_clock clk, int rate) argument
29 switch (clk) {
41 pr_err("%s: requested unknown clock %d\n", __func__, clk);
45 if (qe_clock_is_brg(clk))
46 qe_setbrg(clk, rate, 1);
/arch/sh/kernel/
H A Dlocaltimer.c35 struct clock_event_device *clk = this_cpu_ptr(&local_clockevent); local
38 clk->event_handler(clk);
43 struct clock_event_device *clk)
49 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); local
51 clk->name = "dummy_timer";
52 clk->features = CLOCK_EVT_FEAT_ONESHOT |
55 clk->rating = 400;
56 clk->mult = 1;
57 clk
42 dummy_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *clk) argument
[all...]
/arch/arc/kernel/
H A Ddevtree.c17 #include <asm/clk.h>
44 const void *clk; local
55 clk = of_get_flat_dt_prop(dt_root, "clock-frequency", &len);
56 if (clk)
57 arc_set_core_freq(of_read_ulong(clk, len/4));
/arch/arm/mach-pxa/
H A Dclock-pxa2xx.c19 void clk_pxa2xx_cken_enable(struct clk *clk) argument
21 CKEN |= 1 << clk->cken;
24 void clk_pxa2xx_cken_disable(struct clk *clk) argument
26 CKEN &= ~(1 << clk->cken);
/arch/arm/mach-versatile/include/mach/
H A Dclkdev.h6 struct clk { struct
13 #define __clk_get(clk) ({ 1; })
14 #define __clk_put(clk) do { } while (0)
/arch/m68k/include/asm/
H A Dmcfclk.h9 struct clk;
12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
16 struct clk { struct
24 extern struct clk *mcf_clks[];
33 static struct clk __clk_##clk_bank##_##clk_slot = { \
40 void __clk_init_enabled(struct clk *);
41 void __clk_init_disabled(struct clk *);
44 static struct clk clk_##clk_ref = { \
/arch/mips/ralink/
H A Dclk.c13 #include <linux/clk.h>
19 struct clk { struct
26 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); local
28 if (!clk)
31 clk->cl.dev_id = dev;
32 clk->cl.clk = clk;
42 clk_enable(struct clk *clk) argument
48 clk_disable(struct clk *clk) argument
53 clk_get_rate(struct clk *clk) argument
61 struct clk *clk; local
[all...]
/arch/arm/mach-at91/
H A Dat91x40.c31 int clk_enable(struct clk *clk) argument
36 void clk_disable(struct clk *clk) argument
40 unsigned long clk_get_rate(struct clk *clk) argument
/arch/arm/mach-davinci/
H A Dserial.c28 #include <linux/clk.h>
78 struct clk *clk; local
92 clk = clk_get(dev, NULL);
93 if (IS_ERR(clk)) {
99 clk_prepare_enable(clk);
101 p->uartclk = clk_get_rate(clk);
/arch/arm/mach-imx/
H A Dclk-imx1.c18 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
27 #include "clk.h"
35 static struct clk *clk[IMX1_CLK_MAX]; variable in typeref:struct:clk
47 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
48 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);
49 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
50 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
51 clk[IMX1_CLK_CLK32_PREMUL
[all...]
H A Dclk.c1 #include <linux/clk.h>
6 #include "clk.h"
10 void __init imx_check_clocks(struct clk *clks[], unsigned int count)
16 pr_err("i.MX clk %u: register failed with %ld\n",
20 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
23 struct clk *clk = ERR_PTR(-ENODEV); local
34 clk = of_clk_get_from_provider(&phandle);
37 return clk;
40 struct clk * __ini
43 struct clk *clk; local
[all...]
/arch/arm/mach-lpc32xx/
H A Dclock.h22 struct clk { struct
24 struct clk *parent;
28 int (*set_rate) (struct clk *, unsigned long);
29 unsigned long (*round_rate) (struct clk *, unsigned long);
30 unsigned long (*get_rate) (struct clk *clk);
31 int (*enable) (struct clk *, int);
H A Dserial.c25 #include <linux/clk.h>
75 struct clk *clk; local
83 clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
84 if (!IS_ERR(clk)) {
85 clk_enable(clk);
/arch/arm/mach-mmp/
H A Dclock.c13 #include <linux/clk.h>
19 static void apbc_clk_enable(struct clk *clk) argument
23 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel);
24 __raw_writel(clk_rst, clk->clk_rst);
27 static void apbc_clk_disable(struct clk *clk) argument
29 __raw_writel(0, clk->clk_rst);
37 static void apmu_clk_enable(struct clk *clk) argument
42 apmu_clk_disable(struct clk *clk) argument
54 clk_enable(struct clk *clk) argument
66 clk_disable(struct clk *clk) argument
79 clk_get_rate(struct clk *clk) argument
92 clk_set_rate(struct clk *clk, unsigned long rate) argument
[all...]

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