Searched defs:clk (Results 1 - 25 of 692) sorted by relevance

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/drivers/clk/ti/
H A DMakefile2 obj-y += clk.o autoidle.o clockdomain.o
3 clk-common = dpll.o composite.o divider.o gate.o \
5 obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
6 obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
7 obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o clk-3xxx.o
8 obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk
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H A Dfixed-factor.c18 #include <linux/clk-provider.h>
23 #include <linux/clk/ti.h>
36 struct clk *clk; local
57 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
60 if (!IS_ERR(clk)) {
61 of_clk_add_provider(node, of_clk_src_simple_get, clk);
H A Dautoidle.c18 #include <linux/clk-provider.h>
23 #include <linux/clk/ti.h>
37 static void ti_allow_autoidle(struct clk_ti_autoidle *clk) argument
41 val = ti_clk_ll_ops->clk_readl(clk->reg);
43 if (clk->flags & AUTOIDLE_LOW)
44 val &= ~(1 << clk->shift);
46 val |= (1 << clk->shift);
48 ti_clk_ll_ops->clk_writel(val, clk->reg);
51 static void ti_deny_autoidle(struct clk_ti_autoidle *clk) argument
55 val = ti_clk_ll_ops->clk_readl(clk
107 struct clk_ti_autoidle *clk; local
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H A Dclockdomain.c18 #include <linux/clk-provider.h>
22 #include <linux/clk/ti.h>
29 struct clk *clk; local
38 clk = of_clk_get(node, i);
39 if (IS_ERR(clk)) {
41 __func__, node->full_name, i, PTR_ERR(clk));
44 if (__clk_get_flags(clk) & CLK_IS_BASIC) {
45 pr_warn("can't setup clkdm for basic clk %s\n",
46 __clk_get_name(clk));
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/drivers/clk/
H A Dclk-bcm2835.c20 #include <linux/clk-provider.h>
22 #include <linux/clk/bcm2835.h>
32 struct clk *clk; local
35 clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT,
37 if (IS_ERR(clk))
40 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT,
42 if (IS_ERR(clk))
45 clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT,
47 if (IS_ERR(clk))
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H A Dclk-efm32gg.c9 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
19 static struct clk *clk[37]; variable in typeref:struct:clk
21 .clks = clk,
22 .clk_num = ARRAY_SIZE(clk),
30 for (i = 0; i < ARRAY_SIZE(clk); ++i)
31 clk[i] = ERR_PTR(-ENOENT);
39 clk[clk_HFXO] = clk_register_fixed_rate(NULL, "HFXO", NULL,
42 clk[clk_HFPERCLKUSART
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H A Dclk-conf.c10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clk/clk-conf.h>
16 #include "clk.h"
22 struct clk *clk, *pclk; local
27 pr_err("clk: invalid value of clock-parents property at %s\n",
44 pr_warn("clk: couldn't get parent clock %d for %s\n",
57 clk
84 struct clk *clk; local
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H A Dclk-devres.c7 #include <linux/clk.h>
14 clk_put(*(struct clk **)res);
17 struct clk *devm_clk_get(struct device *dev, const char *id)
19 struct clk **ptr, *clk; local
25 clk = clk_get(dev, id);
26 if (!IS_ERR(clk)) {
27 *ptr = clk;
33 return clk;
39 struct clk **
47 devm_clk_put(struct device *dev, struct clk *clk) argument
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H A Dclk-moxart.c13 #include <linux/clk-provider.h>
21 struct clk *clk, *ref_clk; local
44 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mul, 1);
45 if (IS_ERR(clk)) {
50 clk_register_clkdev(clk, NULL, name);
51 of_clk_add_provider(node, of_clk_src_simple_get, clk);
59 struct clk *clk, *pll_clk; local
87 clk
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/drivers/clk/x86/
H A DMakefile0 clk-x86-lpss-objs := clk-lpt.o
2 obj-$(CONFIG_X86_INTEL_LPSS) += clk-x86-lpss.o
H A Dclk-lpt.c13 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
18 #include <linux/platform_data/clk-lpss.h>
24 struct clk *clk; local
32 clk = clk_register_fixed_rate(&pdev->dev, drvdata->name, NULL,
34 if (IS_ERR(clk))
35 return PTR_ERR(clk);
37 drvdata->clk = clk;
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/drivers/clk/ux500/
H A Du8540_clk.c10 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
14 #include <linux/platform_data/clk-ux500.h>
15 #include "clk.h"
20 struct clk *clk; local
24 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
26 clk_register_clkdev(clk, "soc0_pll", NULL);
28 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
30 clk_register_clkdev(clk, "soc1_pl
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H A Du8500_clk.c10 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
14 #include <linux/platform_data/clk-ux500.h>
15 #include "clk.h"
22 struct clk *clk; local
25 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
27 clk_register_clkdev(clk, "soc0_pll", NULL);
29 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
31 clk_register_clkdev(clk, "soc1_pl
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H A Dabx500-clk.c16 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
20 #include "clk.h"
26 struct clk *clk; local
44 clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK,
46 clk_register_clkdev(clk, "sysclk", "ab8500-usb.0");
47 clk_register_clkdev(clk, "sysclk", "ab-iddet.0");
48 clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0");
49 clk_register_clkdev(clk, "syscl
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/drivers/clk/versatile/
H A Dclk-realview.c9 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
18 #include "clk-icst.h"
53 struct clk *clk; local
56 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
57 clk_register_clkdev(clk, "apb_pclk", NULL);
60 clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT,
62 clk_register_clkdev(clk, NULL, "dev:uart0");
63 clk_register_clkdev(clk, NUL
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H A Dclk-vexpress.c16 #include <linux/clk-provider.h>
20 static struct clk *vexpress_sp810_timerclken[4];
57 struct clk *clk; local
60 clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
62 WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
64 clk = clk_register_fixed_rate(NULL, "v2m:clk_24mhz", NULL,
67 WARN_ON(clk_register_clkdev(clk, NULL,
70 clk = clk_register_fixed_rate(NULL, "v2m:refclk32khz", NULL,
72 WARN_ON(clk_register_clkdev(clk, NUL
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/drivers/clk/sunxi/
H A Dclk-a10-hosc.c17 #include <linux/clk-provider.h>
28 struct clk *clk; local
53 clk = clk_register_composite(NULL, clk_name,
60 if (IS_ERR(clk))
63 of_clk_add_provider(node, of_clk_src_simple_get, clk);
64 clk_register_clkdev(clk, clk_name, NULL);
73 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
H A Dclk-sun8i-apb0.c9 * Based on clk-sun6i-apb0.c
17 #include <linux/clk-provider.h>
29 struct clk *clk; local
43 clk = clk_register_divider(&pdev->dev, clk_name, clk_parent, 0, reg,
45 if (IS_ERR(clk))
46 return PTR_ERR(clk);
48 return of_clk_add_provider(np, of_clk_src_simple_get, clk);
52 { .compatible = "allwinner,sun8i-a23-apb0-clk" },
58 .name = "sun8i-a23-apb0-clk",
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H A Dclk-a20-gmac.c19 #include <linux/clk-provider.h>
33 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
34 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
58 struct clk *clk; local
96 clk = clk_register_composite(NULL, clk_name,
103 if (IS_ERR(clk))
106 of_clk_add_provider(node, of_clk_src_simple_get, clk);
107 clk_register_clkdev(clk, clk_name, NULL);
118 CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
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H A Dclk-sun6i-apb0.c11 #include <linux/clk-provider.h>
17 * The APB0 clk has a configurable divisor.
38 struct clk *clk; local
51 clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent,
54 if (IS_ERR(clk))
55 return PTR_ERR(clk);
57 return of_clk_add_provider(np, of_clk_src_simple_get, clk);
61 { .compatible = "allwinner,sun6i-a31-apb0-clk" },
67 .name = "sun6i-a31-apb0-clk",
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/drivers/gpu/drm/nouveau/core/subdev/clock/
H A Dnva3.h7 u32 clk; member in struct:nva3_clock_info
18 int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags);
19 void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags);
/drivers/gpu/drm/nouveau/
H A Dnouveau_platform.h29 struct clk;
34 struct clk *clk; member in struct:nouveau_platform_gpu
35 struct clk *clk_pwr;
/drivers/usb/phy/
H A Dphy-generic.h9 struct clk *clk; member in struct:usb_phy_generic
/drivers/clk/tegra/
H A Dclk-audio-sync.c17 #include <linux/clk-provider.h>
21 #include "clk.h"
57 struct clk *tegra_clk_register_sync_source(const char *name,
62 struct clk *clk; local
66 pr_err("%s: could not allocate sync source clk\n", __func__);
82 clk = clk_register(NULL, &sync->hw);
83 if (IS_ERR(clk))
86 return clk;
H A Dclk-tegra-fixed.c18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
24 #include <linux/clk/tegra.h>
26 #include "clk.h"
27 #include "clk-id.h"
39 struct clk *clk; local
40 struct clk **dt_clk;
61 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
63 *dt_clk = clk;
84 struct clk *clk; local
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