Searched defs:clk_ctrl (Results 1 - 3 of 3) sorted by relevance

/drivers/cpufreq/
H A Dcris-artpec3-cpufreq.c25 reg_clkgen_rw_clk_ctrl clk_ctrl; local
26 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
27 return clk_ctrl.pll ? 200000 : 6000;
32 reg_clkgen_rw_clk_ctrl clk_ctrl; local
33 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
40 clk_ctrl.pll = 1;
42 clk_ctrl.pll = 0;
43 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
H A Dcris-etraxfs-cpufreq.c25 reg_config_rw_clk_ctrl clk_ctrl; local
26 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
27 return clk_ctrl.pll ? 200000 : 6000;
32 reg_config_rw_clk_ctrl clk_ctrl; local
33 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
40 clk_ctrl.pll = 1;
42 clk_ctrl.pll = 0;
43 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
/drivers/clk/zynq/
H A Dclkc.c179 const char *clk_name1, void __iomem *clk_ctrl,
196 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
198 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
202 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
205 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
177 zynq_clk_register_periph_clk(enum zynq_clk clk0, enum zynq_clk clk1, const char *clk_name0, const char *clk_name1, void __iomem *clk_ctrl, const char **parents, unsigned int two_gates) argument

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