/drivers/clk/ti/ |
H A D | clk.c | 32 * ti_dt_clocks_register - register DT alias clocks during boot 33 * @oclks: list of clocks to register 36 * default, DT clocks are found based on their node name. If any 78 * once all the other clocks have been initialized. 143 * mapping from clocks node to the memory map index. All the clocks 145 * clocks will access their memory maps based on the node layout. 149 struct device_node *clocks; local 151 /* get clocks for this parent */ 152 clocks [all...] |
/drivers/clk/ |
H A D | clk-max-gen.c | 2 * clk-max-gen.c - Generic clock driver for Maxim PMICs clocks 114 struct clk **clocks; local 119 clocks = devm_kzalloc(dev, sizeof(struct clk *) * num_init, GFP_KERNEL); 120 if (!clocks) 150 clocks[i] = max_gen_clk_register(dev, &max_gen_clks[i]); 151 if (IS_ERR(clocks[i])) { 152 ret = PTR_ERR(clocks[i]); 159 platform_set_drvdata(pdev, clocks); 168 of_data->clks = clocks;
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/drivers/staging/media/davinci_vpfe/ |
H A D | vpfe.h | 80 /* number of clocks */ 82 /* clocks used for vpfe capture */ 83 char *clocks[]; member in struct:vpfe_config
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/drivers/ata/ |
H A D | pata_hpt366.c | 124 struct hpt_clock *clocks = ap->host->private_data; local 126 while (clocks->xfer_mode) { 127 if (clocks->xfer_mode == speed) 128 return clocks->timing; 129 clocks++;
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H A D | pata_hpt3x2n.c | 44 struct hpt_clock *clocks[3]; member in struct:hpt_chip 69 /* 66MHz DPLL clocks */ 98 * that matches the speed provided. For the moment the clocks table 105 struct hpt_clock *clocks = hpt3x2n_clocks; local 107 while (clocks->xfer_speed) { 108 if (clocks->xfer_speed == speed) 109 return clocks->timing; 110 clocks++;
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H A D | pata_atp867x.c | 156 unsigned char clocks = clk; local 163 clocks++; 165 switch (clocks) { 167 clocks = 1; 175 clocks = 7; /* 12 clk */ 179 clocks = 0; 184 return clocks << ATP867X_IO_PIOSPD_ACTIVE_SHIFT; 189 unsigned char clocks = clk; local 191 switch (clocks) { 193 clocks [all...] |
H A D | pata_hpt37x.c | 38 struct hpt_clock const *clocks[4]; member in struct:hpt_chip 212 struct hpt_clock *clocks = ap->host->private_data; local 214 while (clocks->xfer_speed) { 215 if (clocks->xfer_speed == speed) 216 return clocks->timing; 217 clocks++; 956 pr_warn("BIOS has not set timing clocks\n"); 974 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { 1023 private_data = (void *)chip_table->clocks[clock_slot]; 1027 * about lack of UDMA133 support on lower clocks [all...] |
/drivers/clk/rockchip/ |
H A D | clk.c | 320 void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks) argument 324 /* Protect the clocks that needs to stay on */ 326 struct clk *clk = __clk_lookup(clocks[i]);
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/drivers/clk/bcm/ |
H A D | clk-kona-setup.c | 512 * placeholders for non-supported clocks. Keep track of the 537 static u32 *parent_process(const char *clocks[], argument 551 if (!clocks) 558 for (clock = clocks; *clock; clock++) 561 orig_count = (u32)(clock - clocks); 564 /* If all clocks are unsupported, we treat it as no clock */ 602 if (clocks[i] != BAD_CLK_NAME) { 603 parent_names[j] = clocks[i]; 615 clk_sel_setup(const char **clocks, struct bcm_clk_sel *sel, argument 625 * by the parent clock's position in the "clocks" lis [all...] |
H A D | clk-kona.h | 85 * CCU policy control for clocks. Clocks can be enabled or disabled 112 * Enabling or disabling clocks with this type of gate is 113 * managed automatically by the hardware. Such clocks can be 115 * of auto-gated clocks can be read from the gate status bit. 210 /* Gate hysteresis for clocks */ 320 * Clocks may have multiple "parent" clocks. If there is more than 322 * clocks is currently in use. The selected clock is indicated in a 325 * available parent clocks. Occasionally the reset value of a 329 * We register all known parent clocks with the common clock code 399 const char *clocks[]; /* mus member in struct:peri_clk_data [all...] |
/drivers/gpu/drm/nouveau/core/subdev/clock/ |
H A D | base.c | 537 struct nouveau_clocks *clocks, 554 clk->domains = clocks; 534 nouveau_clock_create_(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, struct nouveau_clocks *clocks, struct nouveau_pstate *pstates, int nb_pstates, bool allow_reclock, int length, void **object) argument
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/drivers/clk/sunxi/ |
H A D | clk-sunxi.c | 28 /* Maximum number of parents our clocks have */ 335 /* These clocks can only divide, so we will never be able to achieve 401 * sunxi_factors_clk_setup() - Setup function for factor clocks 582 * sunxi_divider_clk_setup() - Setup function for simple divider clocks 722 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks 930 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks 932 * These clocks look something like this 1059 /* Matches for factors clocks */ 1071 /* Matches for divider clocks */ 1088 /* Matches for mux clocks */ 1137 sunxi_init_clocks(const char *clocks[], int nclocks) argument [all...] |
/drivers/mfd/ |
H A D | asic3.c | 87 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)]; member in struct:asic3 665 /* Turn on external clocks and the OWM clock */ 666 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); 667 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); 668 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); 692 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); 693 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); 694 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); 756 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); 760 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX [all...] |
/drivers/gpu/drm/exynos/ |
H A D | exynos_drm_fimc.c | 148 * @clocks: fimc clocks. 162 struct clk *clocks[FIMC_CLKS_MAX]; member in struct:fimc_context 1224 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]); 1225 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]); 1228 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]); 1229 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]); 1608 if (IS_ERR(ctx->clocks[i])) 1610 clk_put(ctx->clocks[i]); 1611 ctx->clocks[ [all...] |
/drivers/gpu/drm/radeon/ |
H A D | btc_dpm.c | 1211 static u32 btc_find_valid_clock(struct radeon_clock_array *clocks, argument 1216 if ((clocks == NULL) || (clocks->count == 0)) 1219 for (i = 0; i < clocks->count; i++) { 1220 if (clocks->values[i] >= requested_clock) 1221 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; 1224 return (clocks->values[clocks->count - 1] < max_clock) ? 1225 clocks [all...] |
/drivers/media/i2c/cx25840/ |
H A D | cx25840-ir.c | 308 u64 clocks; local 310 clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ 311 rem = do_div(clocks, 1000); /* /1000 = cycles */ 313 clocks++; 314 return clocks; 1092 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n", 1116 v4l2_info(sd, "\tNext carrier edge window: 16 clocks " 1159 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
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/drivers/media/pci/cx23885/ |
H A D | cx23888-ir.c | 316 u64 clocks; local 318 clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ 319 rem = do_div(clocks, 1000); /* /1000 = cycles */ 321 clocks++; 322 return clocks; 994 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n", 1018 v4l2_info(sd, "\tNext carrier edge window: 16 clocks " 1063 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
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/drivers/media/platform/exynos4-is/ |
H A D | fimc-is.h | 239 * @clocks: FIMC-LITE gate clock 265 struct clk *clocks[ISS_CLKS_MAX]; member in struct:fimc_is
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/drivers/net/hamradio/ |
H A D | dmascc.c | 168 int clocks; /* see dmascc_cfg documentation */ member in struct:scc_param 574 priv->param.clocks = TCTRxCP | RCRTxCP; 827 /* Configure clocks */ 834 write_scc(priv, R11, priv->param.clocks); 835 if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
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/drivers/gpu/drm/gma500/ |
H A D | psb_intel_sdvo.c | 638 struct psb_intel_sdvo_pixel_clock_range clocks; local 640 BUILD_BUG_ON(sizeof(clocks) != 4); 643 &clocks, sizeof(clocks))) 647 *clock_min = clocks.min * 10; 648 *clock_max = clocks.max * 10;
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/drivers/gpu/drm/i915/ |
H A D | intel_sdvo.c | 705 struct intel_sdvo_pixel_clock_range clocks; local 707 BUILD_BUG_ON(sizeof(clocks) != 4); 710 &clocks, sizeof(clocks))) 714 *clock_min = clocks.min * 10; 715 *clock_max = clocks.max * 10;
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