Searched defs:control (Results 1 - 25 of 317) sorted by relevance

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/drivers/dma/
H A Dcoh901318.h28 * @control: control settings for DMAC
36 u32 control; member in struct:coh901318_lli
/drivers/ata/
H A Dpata_jmicron.c45 u32 control; local
52 pci_read_config_dword(pdev, 0x40, &control);
53 if ((control & port_mask) == 0)
59 if (control & (1 << 23)) {
74 if (control & (1 << 22))
84 if ((control & (1 << 5)) == 0)
86 if (control & (1 << 3)) /* 40/80 pin primary */
H A Dpata_radisys.c44 int control = 0; local
61 control |= 1; /* TIME1 enable */
63 control |= 2; /* IE IORDY */
70 idetm_data |= (control << (4 * adev->devno));
117 int control = 3; /* IORDY|TIME0 */ local
123 control = 1;
125 /* Mask out the relevant control and timing bits we will load. Also
129 idetm_data |= control << (4 * adev->devno);
204 * and then hand over control to libata, for it to do the rest.
H A Dpata_efar.c91 int control = 0; local
106 control |= 1; /* TIME */
108 control |= 2; /* IE */
111 control |= 4; /* PPE */
120 master_data |= control;
128 master_data |= (control << 4);
197 unsigned int control; local
204 control = 3; /* IORDY|TIME1 */
211 control |= 8; /* PIO cycles in PIO0 */
215 master_data |= control <<
[all...]
H A Dpata_it8213.c80 int control = 0; local
95 control |= 1; /* TIME */
97 control |= 2; /* IE */
100 control |= 4; /* PPE */
107 master_data |= control;
114 master_data |= (control << 4);
192 unsigned int control; local
199 control = 3; /* IORDY|TIME1 */
206 control |= 8; /* PIO cycles in PIO0 */
210 master_data |= control <<
[all...]
H A Dpata_mpiix.c40 IDETIM = 0x6C, /* IDE control register */
77 int control = 0; local
92 control |= PPE; /* Enable prefetch/posting for disk */
94 control |= IORDY;
96 control |= FTIM; /* This drive is on the fast timing bank */
101 idetim |= control << (4 * adev->devno);
H A Dpata_oldpiix.c69 int control = 0; local
85 control |= 1; /* TIME */
87 control |= 2; /* IE */
91 control |= 4; /* PPE */
101 idetm_data |= control;
104 idetm_data |= (control << 4);
145 unsigned int control; local
153 control = 3; /* IORDY|TIME0 */
156 control |= 4; /* PPE enable */
163 control |
[all...]
/drivers/clocksource/
H A Dbcm2835_timer.c43 void __iomem *control; member in struct:bcm2835_timer
86 if (readl_relaxed(timer->control) & timer->match_mask) {
87 writel_relaxed(timer->match_mask, timer->control);
126 timer->control = base + REG_CONTROL;
/drivers/ide/
H A Djmicron.c33 u32 control; local
39 pci_read_config_dword(pdev, 0x40, &control);
44 if (control & (1 << 23)) {
59 if (control & (1 << 22))
69 if (control & (1 << 3)) /* 40/80 pin primary */
79 /* Avoid bogus "control reaches end of non-void function" */
H A Dit8213.c36 int control = 0; local
50 control |= 1; /* Programmable timing on */
52 control |= 4; /* ATAPI */
54 control |= 2; /* IORDY */
59 master_data = master_data | (control << 4);
66 master_data = master_data | control;
H A Dslc90e66.c30 int control = 0; local
45 control |= 1; /* Programmable timing on */
47 control |= 4; /* Prefetch, post write */
49 control |= 2; /* IORDY */
55 master_data |= control << 4;
65 master_data |= control;
/drivers/net/ethernet/altera/
H A Daltera_msgdma.c45 msgdma_csroffs(control));
67 msgdma_csroffs(control));
87 tse_clear_bit(priv->rx_dma_csr, msgdma_csroffs(control),
93 tse_set_bit(priv->rx_dma_csr, msgdma_csroffs(control),
99 tse_clear_bit(priv->tx_dma_csr, msgdma_csroffs(control),
105 tse_set_bit(priv->tx_dma_csr, msgdma_csroffs(control),
133 msgdma_descroffs(control));
167 u32 control = (MSGDMA_DESC_CTL_END_ON_EOP local
183 csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control));
[all...]
/drivers/net/irda/
H A Dmcp2120-sir.c102 u8 control[2]; local
120 control[0] = MCP2120_9600;
124 control[0] = MCP2120_19200;
128 control[0] = MCP2120_38400;
132 control[0] = MCP2120_57600;
136 control[0] = MCP2120_115200;
140 control[1] = MCP2120_COMMIT;
142 /* Write control bytes */
143 sirdev_raw_write(dev, control, 2);
H A Dgirbil-sir.c42 #define GIRBIL_ECHO 0x08 /* Echo control characters */
126 u8 control[2]; local
148 control[0] = GIRBIL_9600;
151 control[0] = GIRBIL_19200;
154 control[0] = GIRBIL_38400;
157 control[0] = GIRBIL_57600;
160 control[0] = GIRBIL_115200;
163 control[1] = GIRBIL_LOAD;
165 /* Write control bytes */
166 sirdev_raw_write(dev, control,
209 u8 control = GIRBIL_TXEN | GIRBIL_RXEN; local
[all...]
/drivers/net/usb/
H A Dhuawei_cdc_ncm.c37 struct usb_interface *control; member in struct:huawei_cdc_ncm_state
91 subdriver = usb_cdc_wdm_register(ctx->control,
117 drvstate->subdriver->disconnect(ctx->control);
140 if (intf == ctx->control &&
161 (intf == ctx->control &&
/drivers/net/wireless/brcm80211/brcmsmac/
H A Ddma.h47 u32 control; /* enable, et al */ member in struct:dma64regs
68 uint dmactrlflags; /* dma control flags */
/drivers/parport/
H A Dparport_atari.c8 * with 8 output data lines (D0 - D7), 1 output control line (STROBE)
51 unsigned char control = 0; local
56 control = PARPORT_CONTROL_STROBE;
58 return control;
62 parport_atari_write_control(struct parport *p, unsigned char control) argument
68 if (control & PARPORT_CONTROL_STROBE)
H A Dparport_amiga.c10 * lines (BUSY, POUT, SEL), 1 output control line /STROBE (raised automatically
11 * in hardware when the data register is accessed), and 1 input control line
51 static unsigned char control_amiga_to_pc(unsigned char control) argument
59 static void amiga_write_control(struct parport *p, unsigned char control) argument
61 DPRINTK(KERN_DEBUG "write_control %02x\n",control);
/drivers/dma/ipu/
H A Dipu_irq.c45 unsigned int control; member in struct:ipu_irq_bank
53 .control = IPU_INT_CTRL_1,
56 .control = IPU_INT_CTRL_2,
59 .control = IPU_INT_CTRL_3,
64 .control = IPU_INT_CTRL_4,
67 .control = IPU_INT_CTRL_5,
112 reg = ipu_read_reg(bank->ipu, bank->control);
114 ipu_write_reg(bank->ipu, reg, bank->control);
135 reg = ipu_read_reg(bank->ipu, bank->control);
137 ipu_write_reg(bank->ipu, reg, bank->control);
[all...]
/drivers/hid/
H A Dhid-roccat-common.c78 struct roccat_common2_control control; local
84 &control, sizeof(struct roccat_common2_control));
89 switch (control.value) {
103 control.value);
/drivers/media/pci/saa7134/
H A Dsaa7134-vbi.c85 unsigned long control, base; local
97 control = SAA7134_RS_CONTROL_BURST_16 |
103 saa_writel(SAA7134_RS_CONTROL(2), control);
107 saa_writel(SAA7134_RS_CONTROL(3), control);
/drivers/net/phy/
H A Dlxt.c133 int control; local
142 control = phy_read(phydev, MII_BMCR);
143 if (control < 0)
144 return control;
149 } while (status >= 0 && retry-- && status == control);
/drivers/pci/
H A Dats.c191 u16 control, status; local
199 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
201 if ((control & PCI_PRI_CTRL_ENABLE) ||
209 control |= PCI_PRI_CTRL_ENABLE;
210 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
224 u16 control; local
231 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
232 control &= ~PCI_PRI_CTRL_ENABLE;
233 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
246 u16 control; local
278 u16 control, supported; local
312 u16 control = 0; local
[all...]
/drivers/rtc/
H A Drtc-ds1672.c85 buf[5] = 0; /* set control reg to enable counting */
116 {/* read control */
124 /* read control register */
138 u8 control; local
141 err = ds1672_get_control(client, &control);
145 return sprintf(buf, "%s\n", (control & DS1672_REG_CONTROL_EOSC)
149 static DEVICE_ATTR(control, S_IRUGO, show_control, NULL);
160 u8 control; local
178 /* read control register */
179 err = ds1672_get_control(client, &control);
[all...]
H A Drtc-m48t35.c29 u8 control; member in struct:m48t35_rtc
53 u8 control; local
62 control = readb(&priv->reg->control);
63 writeb(control | M48T35_RTC_READ, &priv->reg->control);
70 writeb(control, &priv->reg->control);
97 u8 control; local
127 control
[all...]

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