Searched defs:d0 (Results 26 - 31 of 31) sorted by relevance

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/arch/mips/alchemy/devboards/
H A Ddb1000.c498 int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1; local
505 d0 = AU1500_GPIO0_INT;
512 d0 = AU1100_GPIO0_INT;
547 d0 = AU1000_GPIO0_INT;
555 d0 = AU1500_GPIO201_INT;
568 d0 = AU1100_GPIO9_INT;
585 irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH);
596 c0, d0, /*s0*/0, 0, 0);
/arch/x86/kernel/
H A Dprocess_64.c61 unsigned long d0, d1, d2, d3, d6, d7; local
105 get_debugreg(d0, 0);
113 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
117 printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
/arch/mn10300/include/asm/
H A Dgdb-stub.h80 u32 d0, d1, d2, d3, a0, a1, a2, a3; member in struct:gdb_regs
/arch/m68k/include/asm/
H A Dm525xsim.h241 moveb #MCFINTC2_VECBASE,%d0
242 moveb %d0,0x16b(%a1) /* interrupt base register */ variable
247 movel #0x001F0021,%d0 /* disable C/I bit */
248 movel %d0,0x84(%a0) /* set CSMR0 */ variable
254 movel 0x180(%a1),%d0 /* get current PLL value */
255 andl #0xfffffffe,%d0 /* PLL bypass first */
256 movel %d0,0x180(%a1) /* set PLL register */ variable
265 movel #0x125a40f0,%d0 /* set for 140MHz */
266 movel %d0,0x180(%a1) /* set PLL register */ variable
267 orl #0x1,%d0
268 movel %d0,0x180(%a1) /* set PLL register */ variable
276 movel %d0,0x8c(%a0) variable
278 movel %d0,0x90(%a0) variable
280 movew %d0,0x96(%a0) variable
286 movel %d0,0x98(%a0) variable
288 movel %d0,0x9c(%a0) variable
290 movew %d0,0xa2(%a0) variable
293 movel %d0,0x18c(%a1) variable
295 movel %d0,0x190(%a1) variable
298 orl %d0,0xc(%a1) /* function GPIO19 */ variable
299 orl %d0,0x8(%a1) /* enable GPIO19 as output */ variable
300 orl %d0,0x4(%a1) /* de-assert IDE reset */ variable
[all...]
H A Dm53xxsim.h162 movel #CORE_SRAM, %d0
163 addl #0x221, %d0
164 movec %d0,%RAMBAR1 variable
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
H A Dpinmux_defs.h269 unsigned int d0 : 1; member in struct:__anon1200

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