/drivers/gpu/drm/nouveau/core/include/subdev/bios/ |
H A D | dp.h | 21 u8 dc; member in struct:nvbios_dpcfg
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/drivers/md/bcache/ |
H A D | debug.h | 20 static inline void bch_data_verify(struct cached_dev *dc, struct bio *bio) {} argument
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H A D | writeback.h | 24 static inline bool bcache_dev_stripe_dirty(struct cached_dev *dc, argument 28 unsigned stripe = offset_to_stripe(&dc->disk, offset); 31 if (atomic_read(dc->disk.stripe_sectors_dirty + stripe)) 34 if (nr_sectors <= dc->disk.stripe_size) 37 nr_sectors -= dc->disk.stripe_size; 42 static inline bool should_writeback(struct cached_dev *dc, struct bio *bio, argument 45 unsigned in_use = dc->disk.c->gc_stats.in_use; 48 test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) || 52 if (dc->partial_stripes_expensive && 53 bcache_dev_stripe_dirty(dc, bi 64 bch_writeback_queue(struct cached_dev *dc) argument 69 bch_writeback_add(struct cached_dev *dc) argument [all...] |
H A D | debug.c | 105 void bch_data_verify(struct cached_dev *dc, struct bio *bio) argument 129 dc->disk.c, 131 bdevname(dc->bdev, name),
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H A D | stats.c | 201 struct cached_dev *dc = container_of(d, struct cached_dev, disk); local 202 mark_cache_stats(&dc->accounting.collector, hit, bypass); 208 struct cached_dev *dc = container_of(d, struct cached_dev, disk); local 209 atomic_inc(&dc->accounting.collector.cache_readaheads); 215 struct cached_dev *dc = container_of(d, struct cached_dev, disk); local 216 atomic_inc(&dc->accounting.collector.cache_miss_collisions); 220 void bch_mark_sectors_bypassed(struct cache_set *c, struct cached_dev *dc, argument 223 atomic_add(sectors, &dc->accounting.collector.sectors_bypassed);
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H A D | writeback.c | 21 static void __update_writeback_rate(struct cached_dev *dc) argument 23 struct cache_set *c = dc->disk.c; 26 div_u64(cache_sectors * dc->writeback_percent, 100); 28 int64_t target = div64_u64(cache_dirty_target * bdev_sectors(dc->bdev), 33 int64_t dirty = bcache_dev_sectors_dirty(&dc->disk); 34 int64_t derivative = dirty - dc->disk.sectors_dirty_last; 38 dc->disk.sectors_dirty_last = dirty; 42 proportional *= dc->writeback_rate_update_seconds; 43 proportional = div_s64(proportional, dc->writeback_rate_p_term_inverse); 45 derivative = div_s64(derivative, dc 74 struct cached_dev *dc = container_of(to_delayed_work(work), local 90 writeback_delay(struct cached_dev *dc, unsigned sectors) argument 101 struct cached_dev *dc; member in struct:dirty_io 131 struct cached_dev *dc = io->dc; local 216 read_dirty(struct cached_dev *dc) argument 329 refill_full_stripes(struct cached_dev *dc) argument 375 refill_dirty(struct cached_dev *dc) argument 399 struct cached_dev *dc = arg; local 468 bch_sectors_dirty_init(struct cached_dev *dc) argument 481 bch_cached_dev_writeback_init(struct cached_dev *dc) argument 500 bch_cached_dev_writeback_start(struct cached_dev *dc) argument [all...] |
/drivers/pwm/ |
H A D | pwm-puv3.c | 44 unsigned long period_cycles, prescale, pv, dc; local 63 dc = OST_PWMDCCR_FDCYCLE; 65 dc = (pv + 1) * duty_ns / period_ns; 74 writel(pv - dc, puv3->base + OST_PWM_DCCR);
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H A D | pwm-pxa.c | 68 unsigned long period_cycles, prescale, pv, dc; local 88 dc = PWMDCR_FD; 90 dc = (pv + 1) * duty_ns / period_ns; 100 writel(dc, pc->mmio_base + offset + PWMDCR);
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H A D | pwm-bcm-kona.c | 99 unsigned long prescale = PRESCALE_MIN, pc, dc; local 121 dc = div64_u64(val, div); 124 if (pc < PERIOD_COUNT_MIN || dc < DUTY_CYCLE_HIGH_MIN) 127 /* If pc and dc are in bounds, the calculation is done */ 128 if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX) 131 /* Otherwise, increase prescale and recalculate pc and dc */ 145 writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
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H A D | pwm-spear.c | 82 unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc; local 86 * Find pv, dc and prescale to suit duty_ns and period_ns. This is done 102 dc = div64_u64(val, div); 105 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY) 109 * if pv and dc have crossed their upper limit, then increase 110 * prescale and recalculate pv and dc. 112 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) { 130 spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc);
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H A D | pwm-vt8500.c | 85 unsigned long period_cycles, prescale, pv, dc; local 114 dc = c; 122 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
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/drivers/scsi/esas2r/ |
H A D | esas2r_targdb.c | 121 dc) 127 if (dc->curr_virt_id >= ESAS2R_MAX_TARGETS) { 133 t = a->targetdb + dc->curr_virt_id; 140 esas2r_hdebug("add RAID %s, T:%d", dc->raid_grp_name, 145 if (dc->interleave == 0 146 || dc->block_size == 0) { 156 t->block_size = dc->block_size; 157 t->inter_byte = dc->interleave; 158 t->inter_block = dc->interleave / dc 119 esas2r_targ_db_add_raid(struct esas2r_adapter *a, struct esas2r_disc_context * dc) argument 172 esas2r_targ_db_add_pthru(struct esas2r_adapter *a, struct esas2r_disc_context *dc, u8 *ident, u8 ident_len) argument [all...] |
H A D | esas2r_disc.c | 291 struct esas2r_disc_context *dc = &a->disc_ctx; local 298 dc->disc_evt |= disc_evt; 314 struct esas2r_disc_context *dc = &a->disc_ctx; local 326 if (dc->disc_evt) { 352 esas2r_trace("disc_evt: %d", dc->disc_evt); 354 dc->flags = 0; 357 dc->flags |= DCF_POLLED; 359 rq->interrupt_cx = dc; 363 if (dc->disc_evt & DCDE_DEV_SCAN) { 364 dc 389 struct esas2r_disc_context *dc = local 505 struct esas2r_disc_context *dc = local 520 struct esas2r_disc_context *dc = local 551 struct esas2r_disc_context *dc = local 580 struct esas2r_disc_context *dc = local 627 struct esas2r_disc_context *dc = local 690 struct esas2r_disc_context *dc = local 742 struct esas2r_disc_context *dc = local 791 struct esas2r_disc_context *dc = local 828 struct esas2r_disc_context *dc = local 884 struct esas2r_disc_context *dc = local 942 struct esas2r_disc_context *dc = local 1046 struct esas2r_disc_context *dc = local 1085 struct esas2r_disc_context *dc = local [all...] |
H A D | esas2r_int.c | 392 struct esas2r_disc_context *dc; local 404 dc = (struct esas2r_disc_context *)rq->interrupt_cx; 406 dc->disc_evt = 0;
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/drivers/gpu/drm/tegra/ |
H A D | rgb.c | 13 #include "dc.h" 17 struct tegra_dc *dc; member in struct:tegra_rgb 78 static void tegra_dc_write_regs(struct tegra_dc *dc, argument 85 tegra_dc_writel(dc, table[i].value, table[i].offset); 96 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 99 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); 102 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); 105 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); 110 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); 114 tegra_dc_writel(rgb->dc, valu 218 tegra_dc_rgb_probe(struct tegra_dc *dc) argument 263 tegra_dc_rgb_remove(struct tegra_dc *dc) argument 277 tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc) argument 304 tegra_dc_rgb_exit(struct tegra_dc *dc) argument [all...] |
H A D | drm.c | 664 struct tegra_dc *dc = to_tegra_dc(crtc); local 666 if (dc->pipe == pipe) 682 struct tegra_dc *dc = to_tegra_dc(crtc); local 687 tegra_dc_enable_vblank(dc); 695 struct tegra_dc *dc = to_tegra_dc(crtc); local 698 tegra_dc_disable_vblank(dc); 855 { .compatible = "nvidia,tegra20-dc", }, 859 { .compatible = "nvidia,tegra30-dc", }, 866 { .compatible = "nvidia,tegra124-dc", },
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H A D | drm.h | 136 static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value, argument 139 writel(value, dc->regs + (reg << 2)); 142 static inline unsigned long tegra_dc_readl(struct tegra_dc *dc, argument 145 return readl(dc->regs + (reg << 2)); 171 /* from dc.c */ 172 void tegra_dc_enable_vblank(struct tegra_dc *dc); 173 void tegra_dc_disable_vblank(struct tegra_dc *dc); 258 int tegra_dc_rgb_probe(struct tegra_dc *dc); 259 int tegra_dc_rgb_remove(struct tegra_dc *dc); 260 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); [all...] |
/drivers/misc/mic/host/ |
H A D | mic_virtio.h | 88 * @dc - Virtio device control fields. 107 struct mic_device_ctrl *dc; member in struct:mic_vdev
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H A D | mic_debugfs.c | 198 struct mic_device_ctrl *dc; local 221 dc = (void *)d + mic_aligned_desc_size(d); 254 seq_printf(s, "Config Change %d ", dc->config_change); 255 seq_printf(s, "Vdev reset %d\n", dc->vdev_reset); 256 seq_printf(s, "Guest Ack %d ", dc->guest_ack); 257 seq_printf(s, "Host ack %d\n", dc->host_ack); 259 dc->used_address_updated); 260 seq_printf(s, "Vdev 0x%llx\n", dc->vdev); 261 seq_printf(s, "c2h doorbell %d ", dc->c2h_vdev_db); 262 seq_printf(s, "h2c doorbell %d\n", dc [all...] |
H A D | mic_virtio.c | 185 s8 db = mvdev->dc->h2c_vdev_db; 401 mvdev->dc->used_address_updated = 0; 423 mvdev->dc->vdev_reset = 0; 424 mvdev->dc->host_ack = 1; 458 if (mvdev->dc->used_address_updated) 461 if (mvdev->dc->vdev_reset) 502 mvdev->dc->config_change = MIC_VIRTIO_PARAM_CONFIG_CHANGED; 507 mvdev->dc->guest_ack, msecs_to_jiffies(100)); 514 mvdev->dc->config_change = 0; 515 mvdev->dc 603 struct mic_device_ctrl *dc; local [all...] |
/drivers/md/ |
H A D | dm-delay.c | 49 struct delay_c *dc = (struct delay_c *)data; local 51 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); 54 static void queue_timeout(struct delay_c *dc, unsigned long expires) argument 56 mutex_lock(&dc->timer_lock); 58 if (!timer_pending(&dc->delay_timer) || expires < dc->delay_timer.expires) 59 mod_timer(&dc->delay_timer, expires); 61 mutex_unlock(&dc->timer_lock); 76 static struct bio *flush_delayed_bios(struct delay_c *dc, in argument 114 struct delay_c *dc; local 129 struct delay_c *dc; local 216 struct delay_c *dc = ti->private; local 228 delay_bio(struct delay_c *dc, int delay, struct bio *bio) argument 259 struct delay_c *dc = ti->private; local 268 struct delay_c *dc = ti->private; local 275 struct delay_c *dc = ti->private; local 296 struct delay_c *dc = ti->private; local 319 struct delay_c *dc = ti->private; local [all...] |
/drivers/i2c/busses/ |
H A D | i2c-ibm_iic.c | 184 u8 dc; local 193 dc = in_8(&iic->directcntl); 194 if (!DIRCTNL_FREE(dc)){ 202 dc = in_8(&iic->directcntl); 203 if (DIRCTNL_FREE(dc)) 207 dc ^= DIRCNTL_SCC; 208 out_8(&iic->directcntl, dc); 210 dc ^= DIRCNTL_SCC; 211 out_8(&iic->directcntl, dc);
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/drivers/infiniband/hw/qib/ |
H A D | qib_diag.c | 80 struct qib_diag_client *dc; local 82 dc = client_pool; 83 if (dc) 85 client_pool = dc->next; 88 dc = kmalloc(sizeof *dc, GFP_KERNEL); 90 if (dc) { 91 dc->next = NULL; 92 dc->dd = dd; 93 dc 102 return_client(struct qib_diag_client *dc) argument 185 struct qib_diag_client *dc; local 509 struct qib_diag_client *dc; local 763 struct qib_diag_client *dc = fp->private_data; local 839 struct qib_diag_client *dc = fp->private_data; local [all...] |
/drivers/staging/imx-drm/ |
H A D | ipuv3-crtc.c | 47 struct ipu_dc *dc; member in struct:ipu_crtc 71 ipu_dc_enable_channel(ipu_crtc->dc); 85 ipu_dc_disable_channel(ipu_crtc->dc); 188 ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced, 318 if (!IS_ERR_OR_NULL(ipu_crtc->dc)) 319 ipu_dc_put(ipu_crtc->dc); 330 ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc); 331 if (IS_ERR(ipu_crtc->dc)) { 332 ret = PTR_ERR(ipu_crtc->dc); [all...] |
/drivers/dma/ |
H A D | txx9dmac.h | 196 static inline bool is_dmac64(const struct txx9dmac_chan *dc) argument 198 return __is_dmac64(dc->ddev); 240 static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc) argument 242 return (dc->ccr & TXX9_DMA_CCR_INTENT) != 0; 245 static inline void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc) argument 247 dc->ccr |= TXX9_DMA_CCR_INTENT; 255 static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc) argument 257 dc->ccr |= TXX9_DMA_CCR_SMPCHN; 268 static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc) argument 273 static void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc) argument 286 txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc) argument [all...] |