/arch/mn10300/include/asm/ |
H A D | div64.h | 79 unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div) argument 84 "divu %3,%0 \n" /* val = MDR:val/div; 85 * MDR = MDR:val%div */ 87 : "0"(val), "ir"(mult), "r"(div) 100 signed __muldiv64s(signed val, signed mult, signed div) argument 105 "div %3,%0 \n" /* val = MDR:val/div; 106 * MDR = MDR:val%div */ 108 : "0"(val), "ir"(mult), "r"(div)
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/arch/arm/mach-shmobile/ |
H A D | clock.h | 26 int div; member in struct:clk_ratio 32 .div = d, \ 52 (p)->div = d; \
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H A D | timer.c | 27 unsigned int mult, unsigned int div) 37 unsigned int value = HZ * div / mult; 26 shmobile_setup_delay_hz(unsigned int max_cpu_core_hz, unsigned int mult, unsigned int div) argument
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/arch/powerpc/boot/ |
H A D | cuboot-52xx.c | 27 int div; local 50 div = in_8(reg + 0x204) & 0x0020 ? 8 : 4; 51 sysfreq = bd.bi_busfreq * div;
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H A D | mpc8xx.c | 27 int mfi, mfn, mfd, pdf, div; local 46 div = (plprcr >> 20) & 3;
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/arch/x86/realmode/rm/ |
H A D | wakemain.c | 17 u16 div = 1193181/hz; local 21 outb(div, 0x42); /* LSB of counter */ 23 outb(div >> 8, 0x42); /* MSB of counter */
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/arch/arm/mach-at91/ |
H A D | clock.h | 23 unsigned div; /* parent clock divider */ member in struct:clk
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/arch/arm/mach-rpc/include/mach/ |
H A D | acornfb.h | 85 u_int div; local 88 div = var->pixclock / 9090; /*9921*/ 91 if (div == 0) 92 div = 1; 93 if (div > 8) 94 div = 8; 97 switch (div) { 136 vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div);
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/arch/arm/mach-imx/ |
H A D | clk-fixup-div.c | 63 struct clk_divider *div = to_clk_div(hw); local 73 if (value > div_mask(div)) 74 value = div_mask(div); 76 spin_lock_irqsave(div->lock, flags); 78 val = readl(div->reg); 79 val &= ~(div_mask(div) << div->shift); 80 val |= value << div->shift; 82 writel(val, div->reg); 84 spin_unlock_irqrestore(div [all...] |
H A D | clk-busy.c | 33 struct clk_divider div; member in struct:clk_busy_divider 41 struct clk_divider *div = container_of(hw, struct clk_divider, hw); local 43 return container_of(div, struct clk_busy_divider, div); 51 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); 59 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); 68 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); 96 busy->div.reg = reg; 97 busy->div.shift = shift; 98 busy->div [all...] |
H A D | clk.h | 128 const char *parent, unsigned int mult, unsigned int div) 131 CLK_SET_RATE_PARENT, mult, div); 127 imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) argument
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H A D | clk-pllv3.c | 105 u32 div = readl_relaxed(pll->base) & pll->div_mask; local 107 return (div == 1) ? parent_rate * 22 : parent_rate * 20; 123 u32 val, div; local 126 div = 1; 128 div = 0; 134 val |= div; 152 u32 div = readl_relaxed(pll->base) & pll->div_mask; local 154 return parent_rate * div / 2; 163 u32 div; local 169 div 180 u32 val, div; local 208 u32 div = readl_relaxed(pll->base) & pll->div_mask; local 219 u32 div; local 243 u32 val, div; local [all...] |
/arch/arm/mach-omap2/ |
H A D | clkt2xxx_dpllcore.c | 115 u32 cur_rate, low, mult, div, valid_rate, done_rate; local 144 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); 156 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
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H A D | clkt_clksel.c | 131 for (clkr = clks->rates; clkr->div; clkr++) { 139 if (!clkr->div) { 147 return clkr->div; 153 * @div: integer divisor to search for 160 static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) argument 167 WARN_ON(div == 0); 174 for (clkr = clks->rates; clkr->div; clkr++) { 178 if (clkr->div == div) 182 if (!clkr->div) { 359 u32 div = 0; local [all...] |
H A D | clock.h | 128 * @div: clock divisor corresponding to @val 134 * @div is the divisor that should be applied to the parent clock's rate 139 u8 div; member in struct:clksel_rate
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H A D | gpmc-onenand.c | 171 int div, gpmc_clk_ns; local 218 div = gpmc_calc_divider(min_gpmc_clk_period); 219 gpmc_clk_ns = gpmc_ticks_to_ns(div);
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/arch/cris/arch-v32/kernel/ |
H A D | time.c | 308 reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ; local 313 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
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/arch/m68k/atari/ |
H A D | debug.c | 219 int clksrc, clkmode, div, reg3, reg5; local 229 div = div_table[baud]; 236 div = 0; 253 SCC_WRITE(12, div); /* BRG value */ 256 SCC_WRITE(14, brgsrc_table[baud] | (div ? 1 : 0)); 269 int div; local 276 div = ACIA_DIV64; /* really 7812.5 bps */ 278 div = ACIA_DIV1; /* really 500 kbps (does that work??) */ 280 div = ACIA_DIV16; /* 31250 bps, standard for MIDI */ 283 acia.mid_ctrl = div | csiz [all...] |
/arch/m68k/fpsp040/ |
H A D | decbin.S | 62 | Clean up and return. Check if the final mul or div resulted 385 fdivx %fp1,%fp0 |div mantissa by 10**(no_bits_shifted) 484 div: label 493 | If the final mul/div in decbin incurred an inex exception,
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/arch/m68k/math-emu/ |
H A D | multi_arith.h | 131 #define fp_div64(quot, rem, srch, srcl, div) \ 133 : "dm" (div), "1" (srch), "0" (srcl)) 182 struct fp_ext *div) 190 /* the algorithm below requires dest to be smaller than div, 192 if (src->mant.m64 >= div->mant.m64) { 193 fp_sub64(src->mant, div->mant); 209 dummy = div->mant.m32[1] / div->mant.m32[0] + 1; 215 if (src->mant.m32[0] == div->mant.m32[0]) { 216 fp_div64(first, rem, 0, src->mant.m32[1], div 181 fp_dividemant(union fp_mant128 *dest, struct fp_ext *src, struct fp_ext *div) argument [all...] |
/arch/mips/ralink/ |
H A D | mt7620.c | 141 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) argument 147 do_div(t, div); 185 u32 div; local 200 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & 203 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); 205 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); 228 u32 div; local 233 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & 236 return mt7620_calc_rate(pll_rate, mul, div); 261 u32 div; local [all...] |
/arch/unicore32/kernel/ |
H A D | clock.c | 102 unsigned long div; member in struct:__anon3024 104 {.rate = 25175000, .cfg = 0x00002001, .div = 0x9}, 105 {.rate = 31500000, .cfg = 0x00002001, .div = 0x7}, 106 {.rate = 40000000, .cfg = 0x00003801, .div = 0x9}, 107 {.rate = 49500000, .cfg = 0x00003801, .div = 0x7}, 108 {.rate = 65000000, .cfg = 0x00002c01, .div = 0x4}, 109 {.rate = 78750000, .cfg = 0x00002400, .div = 0x7}, 110 {.rate = 108000000, .cfg = 0x00002c01, .div = 0x2}, 111 {.rate = 106500000, .cfg = 0x00003c01, .div = 0x3}, 112 {.rate = 50650000, .cfg = 0x00106400, .div [all...] |
/arch/arm/mach-s3c24xx/ |
H A D | iotiming-s3c2410.c | 108 unsigned int div = to_div(cyc, hclk_tns); local 111 s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n", 112 __func__, cyc, hclk_tns, shift, div); 114 switch (div) { 156 unsigned int div = to_div(cyc, hclk_tns); local 159 s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n", 160 __func__, cyc, nwait_en, hclk_tns, div); 163 if (nwait_en && div < 4) 164 div = 4; 166 switch (div) { [all...] |
/arch/m68k/coldfire/ |
H A D | m53xx.c | 539 int clock_limp(int div) argument 544 if (div < MIN_LPD) 545 div = MIN_LPD; 546 if (div > MAX_LPD) 547 div = MAX_LPD; 554 writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR); 558 return (FREF/(3*(1 << div)));
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/arch/mips/ath79/ |
H A D | clock.c | 59 u32 div; local 65 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; 66 freq = div * ref_rate; 68 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; 69 cpu_rate = freq / div; 71 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; 72 ddr_rate = freq / div; 74 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; 75 ahb_rate = cpu_rate / div; 94 u32 div; local 130 u32 div; local [all...] |