Searched defs:enable (Results 1 - 25 of 130) sorted by relevance

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/arch/arm/mach-omap1/
H A Dflash.c18 void omap1_set_vpp(struct platform_device *pdev, int enable) argument
23 if (enable)
/arch/arm/mach-w90x900/
H A Dclock.h15 void nuc900_clk_enable(struct clk *clk, int enable);
16 void nuc900_subclk_enable(struct clk *clk, int enable);
21 void (*enable)(struct clk *, int enable); member in struct:clk
26 .enable = nuc900_clk_enable, \
32 .enable = nuc900_subclk_enable, \
H A Dclock.c38 (clk->enable)(clk, 1);
53 (clk->enable)(clk, 0);
64 void nuc900_clk_enable(struct clk *clk, int enable) argument
71 if (enable)
79 void nuc900_subclk_enable(struct clk *clk, int enable) argument
86 if (enable)
H A Dirq.c36 void (*enable)(struct group_irq *, int enable); member in struct:group_irq
43 .enable = nuc900_group_enable, \
47 static void nuc900_group_enable(struct group_irq *gpirq, int enable);
64 (group_irq->enable)(group_irq, 1);
78 (group_irq->enable)(group_irq, 0);
82 static void nuc900_group_enable(struct group_irq *gpirq, int enable) argument
89 if (enable)
/arch/m68k/include/asm/
H A Dmcfclk.h12 void (*enable)(struct clk *); member in struct:clk_ops
/arch/powerpc/sysdev/
H A Dgrackle.c30 static inline void grackle_set_stg(struct pci_controller* bp, int enable) argument
36 val = enable? (val | GRACKLE_PICR1_STG) :
43 static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) argument
49 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
/arch/arm/mach-lpc32xx/
H A Dclock.h31 int (*enable) (struct clk *, int); member in struct:clk
/arch/arm/mach-omap2/
H A Dmcbsp.c31 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
39 static int omap3_enable_st_clock(unsigned int id, bool enable) argument
45 if (enable)
/arch/arm/mach-pxa/
H A Dclock.h5 void (*enable)(struct clk *); member in struct:clkops
/arch/arm/mach-sa1100/
H A Dclock.c20 void (*enable)(struct clk *); member in struct:clkops
68 clk->ops->enable(clk);
91 .enable = clk_gpio27_enable,
H A Dh3100.c53 static void h3100_lcd_power(int enable) argument
58 gpio_set_value(H3100_GPIO_LCD_3V_ON, enable);
59 gpio_set_value(H3XXX_EGPIO_LCD_ON, enable);
H A Dh3600.c55 static void h3600_lcd_power(int enable) argument
60 gpio_direction_output(H3XXX_EGPIO_LCD_ON, enable);
61 gpio_direction_output(H3600_EGPIO_LCD_PCI, enable);
62 gpio_direction_output(H3600_EGPIO_LCD_5V_ON, enable);
63 gpio_direction_output(H3600_EGPIO_LVDD_ON, enable);
/arch/arm/mach-shmobile/
H A Dclock.c31 int nr_clks, bool enable)
42 if (enable)
30 shmobile_clk_workaround(const struct clk_name *clks, int nr_clks, bool enable) argument
/arch/mips/alchemy/common/
H A Dvss.c21 /* enable a block as outlined in the databook */
26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */
32 /* enable footers in sequence */
48 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */
69 void au1300_vss_block_control(int block, int enable) argument
78 if (enable)
/arch/mips/bcm63xx/
H A Dcs.c123 * set cs status (enable/disable)
125 int bcm63xx_set_cs_status(unsigned int cs, int enable) argument
135 if (enable)
/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-spi.c81 union cvmx_pko_reg_crc_enable enable; local
89 enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE);
90 enable.s.enable |= 0xffff << (interface * 16);
91 cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64);
98 * Bringup and enable a SPI interface. After this call packet I/O
/arch/sh/include/asm/
H A Dperf_event.h13 void (*enable)(struct hw_perf_event *, int); member in struct:sh_pmu
/arch/x86/realmode/rm/
H A Dwakemain.c12 u8 enable; local
15 enable = 0x00; /* Turn off speaker */
26 enable = 0x03; /* Turn on speaker */
30 outb(enable, 0x61); /* Enable timer 2 output to speaker */
/arch/xtensa/variants/s6000/
H A Dirq.c52 static void irq_set(unsigned int irq, int enable) argument
59 en = enable ? scp_to_intc_enable[irq] : 0;
/arch/arm/mach-davinci/
H A Dpsc.c78 unsigned int id, bool enable, u32 flags)
93 if (!enable) {
77 davinci_psc_config(unsigned int domain, unsigned int ctlr, unsigned int id, bool enable, u32 flags) argument
/arch/arm/mach-mmp/
H A Dclock.h12 void (*enable)(struct clk *); member in struct:clkops
23 uint32_t enable_val; /* value for clock enable (APMU) */
/arch/blackfin/mach-common/
H A Dclock.h10 int (*enable)(struct clk *clk); member in struct:clk_ops
/arch/mips/include/asm/
H A Dclock.h13 void (*enable) (struct clk *clk); member in struct:clk_ops
/arch/alpha/oprofile/
H A Dop_impl.h33 unsigned long enable; member in struct:op_register_config
/arch/arm/include/asm/mach/
H A Ddma.h20 void (*enable)(unsigned int, dma_t *); /* mandatory */ member in struct:dma_ops

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