Searched defs:intr_cfg_reg (Results 1 - 1 of 1) sorted by relevance

/drivers/pinctrl/qcom/
H A Dpinctrl-msm.h42 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
52 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
58 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
59 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
60 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
75 s16 intr_cfg_reg; member in struct:msm_pingroup

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