Searched defs:mask (Results 26 - 50 of 690) sorted by relevance

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/arch/sh/include/asm/
H A Datomic-llsc.h60 static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) argument
70 : "r" (~mask), "r" (&v->counter)
74 static inline void atomic_set_mask(unsigned int mask, atomic_t *v) argument
84 : "r" (mask), "r" (&v->counter)
H A Dheartbeat.h14 unsigned int mask; member in struct:heartbeat_data
/arch/tile/include/asm/
H A Dbitops_32.h22 unsigned long _atomic_or(volatile unsigned long *p, unsigned long mask);
23 unsigned long _atomic_andn(volatile unsigned long *p, unsigned long mask);
24 unsigned long _atomic_xor(volatile unsigned long *p, unsigned long mask);
85 unsigned long mask = BIT_MASK(nr); local
88 return (_atomic_or(addr, mask) & mask) != 0;
101 unsigned long mask = BIT_MASK(nr); local
104 return (_atomic_andn(addr, mask) & mask) != 0;
118 unsigned long mask local
[all...]
/arch/alpha/kernel/
H A Dirq_pyxis.c20 /* Note mask bit is true for ENABLED irqs. */
24 pyxis_update_irq_hw(unsigned long mask) argument
26 *(vulp)PYXIS_INT_MASK = mask;
47 unsigned long mask = cached_irq_mask &= ~bit; local
50 *(vulp)PYXIS_INT_MASK = mask;
/arch/arm/include/asm/
H A Dsmp_plat.h95 u32 mask; /* used by sleep.S */ member in struct:mpidr_hash
/arch/arm/lib/
H A Dbacktrace.S22 #define mask r7 define
36 ARM( moveq mask, #0xfc000003 )
37 THUMB( moveq mask, #0xfc000000 )
38 THUMB( orreq mask, #0x03 )
39 movne mask, #0 @ mask for 32-bit
61 for_each_frame: tst frame, mask @ Check for address exceptions
68 bic sv_pc, sv_pc, mask @ mask PC/LR for the mode
78 bic r1, r1, mask
[all...]
/arch/arm/mach-davinci/
H A Dmux.c37 unsigned int mask, warn = 0; local
63 if (cfg->mask) {
69 mask = (cfg->mask << cfg->mask_offset);
70 tmp1 = reg_orig & mask;
71 reg = reg_orig & ~mask;
/arch/arm/mach-omap2/
H A Dprcm_mpu44xx.c41 u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) argument
46 v &= ~mask;
/arch/arm/mach-s3c64xx/
H A Dirq-pm.c55 u32 mask; member in struct:irq_grp_save
80 grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
101 __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
/arch/arm/mach-shmobile/
H A Dplatsmp-scu.c72 unsigned long mask = SCU_PM_POWEROFF << (cpu * 8); local
74 if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
/arch/cris/include/asm/
H A Dbitops.h75 unsigned int mask, retval; local
80 mask = 1 << (nr & 0x1f);
82 retval = (mask & *adr) != 0;
83 *adr |= mask;
99 unsigned int mask, retval; local
104 mask = 1 << (nr & 0x1f);
106 retval = (mask & *adr) != 0;
107 *adr &= ~mask;
123 unsigned int mask, retval; local
127 mask
[all...]
/arch/ia64/sn/kernel/sn2/
H A Dptc_deadlock.S33 mask = r18 define
38 movl mask=WRITECOUNTMASK
52 and scr2=scr1,mask;; // mask of writecount bits
67 and scr2=scr1,mask;; // mask of writecount bits
78 and scr2=scr1,mask;; // mask of writecount bits
/arch/m32r/include/asm/
H A Dbitops.h46 __u32 mask; local
52 mask = (1 << (nr & 0x1F));
61 : "r" (a), "r" (mask)
82 __u32 mask; local
88 mask = (1 << (nr & 0x1F));
98 : "r" (a), "r" (~mask)
118 __u32 mask; local
124 mask = (1 << (nr & 0x1F));
133 : "r" (a), "r" (mask)
152 __u32 mask, oldbi local
187 __u32 mask, oldbit; local
224 __u32 mask, oldbit; local
[all...]
/arch/m68k/68000/
H A Dints.c74 * into one vector and look in the blasted mask register...
80 int mask; local
88 mask = 0x00000001;
91 mask = 0x00000010;
96 mask = 0x00000100;
99 mask = 0x00001000;
106 mask = 0x00010000;
109 mask = 0x00100000;
114 mask = 0x01000000;
117 mask
[all...]
/arch/m68k/include/asm/
H A Dnettel.h56 static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) argument
60 ppdata = (ppdata & ~mask) | bits;
93 static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) argument
95 write((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
/arch/metag/include/asm/
H A Dbitops.h15 unsigned long mask = 1UL << (bit & 31); local
21 *p |= mask;
28 unsigned long mask = 1UL << (bit & 31); local
34 *p &= ~mask;
41 unsigned long mask = 1UL << (bit & 31); local
47 *p ^= mask;
55 unsigned long mask = 1UL << (bit & 31); local
61 if (!(old & mask)) {
63 *p = old | mask;
67 return (old & mask) !
75 unsigned long mask = 1UL << (bit & 31); local
95 unsigned long mask = 1UL << (bit & 31); local
[all...]
/arch/mips/ath79/
H A Dcommon.c59 void ath79_device_reset_set(u32 mask) argument
82 ath79_reset_wr(reg, t | mask);
87 void ath79_device_reset_clear(u32 mask) argument
110 ath79_reset_wr(reg, t & ~mask);
H A Dearly_printk.c23 static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) argument
29 if ((t & mask) == val)
/arch/mips/cavium-octeon/executive/
H A Dcvmx-interrupt-rsl.c52 int mask; local
60 mask = 0xf; /* Set enables for 4 ports */
62 mask = 0x7; /* Set enables for 3 ports */
66 csr.s.txpsh = mask;
67 csr.s.txpop = mask;
68 csr.s.ovrflw = mask;
/arch/mips/include/asm/mach-cavium-octeon/
H A Ddma-coherence.h49 static inline int plat_dma_supported(struct device *dev, u64 mask) argument
/arch/mips/include/asm/mach-ip32/
H A Ddma-coherence.h70 static inline int plat_dma_supported(struct device *dev, u64 mask) argument
73 * we fall back to GFP_DMA when the mask isn't all 1s,
77 if (mask < DMA_BIT_MASK(24))
/arch/mips/include/asm/mach-jazz/
H A Ddma-coherence.h38 static inline int plat_dma_supported(struct device *dev, u64 mask) argument
41 * we fall back to GFP_DMA when the mask isn't all 1s,
45 if (mask < DMA_BIT_MASK(24))
/arch/mips/include/asm/mach-loongson/
H A Ddma-coherence.h59 static inline int plat_dma_supported(struct device *dev, u64 mask) argument
62 * we fall back to GFP_DMA when the mask isn't all 1s,
66 if (mask < DMA_BIT_MASK(24))
/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dmsp_regops.h72 u32 const mask,
88 : "ir" (~mask), "ir" (value), "m" (*addr));
95 u32 const mask)
109 : "ir" (mask), "m" (*addr));
116 u32 const mask)
130 : "ir" (~mask), "m" (*addr));
137 u32 const mask)
151 : "ir" (mask), "m" (*addr));
158 u32 const mask)
166 " and %0, %2 # mask \
71 set_value_reg32(volatile u32 *const addr, u32 const mask, u32 const value) argument
94 set_reg32(volatile u32 *const addr, u32 const mask) argument
115 clear_reg32(volatile u32 *const addr, u32 const mask) argument
136 toggle_reg32(volatile u32 *const addr, u32 const mask) argument
157 read_reg32(volatile u32 *const addr, u32 const mask) argument
[all...]
/arch/mips/kernel/
H A Dirq-gt641xx.c47 u32 mask; local
50 mask = GT_READ(GT_INTRMASK_OFS);
51 mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
52 GT_WRITE(GT_INTRMASK_OFS, mask);
59 u32 cause, mask; local
62 mask = GT_READ(GT_INTRMASK_OFS);
63 mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
64 GT_WRITE(GT_INTRMASK_OFS, mask);
75 u32 mask; local
78 mask
94 u32 cause, mask; local
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