Searched defs:mmr_base (Results 1 - 3 of 3) sorted by relevance

/drivers/char/
H A Dmbcs.c203 void *mmr_base; local
208 mmr_base = soft->mmr_base;
219 mbcs_getdma_set(mmr_base, tiocx_dma_addr(gdma->hostAddr),
233 cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
235 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
243 void *mmr_base; local
248 mmr_base = soft->mmr_base;
259 mbcs_putdma_set(mmr_base, tiocx_dma_add
284 void *mmr_base = soft->mmr_base; local
483 uint64_t mmr_base; local
531 void *mmr_base; local
671 void *mmr_base = soft->mmr_base; local
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H A Dmbcs.h66 #define MBCS_MMR_ADDR(mmr_base, offset)((uint64_t *)(mmr_base + offset))
67 #define MBCS_MMR_SET(mmr_base, offset, value) { \
69 mbcs_mmr_set_u64p = (uint64_t *)(mmr_base + offset); \
73 #define MBCS_MMR_GET(mmr_base, offset) *(uint64_t *)(mmr_base + offset)
74 #define MBCS_MMR_ZERO(mmr_base, offset) MBCS_MMR_SET(mmr_base, offset, 0)
522 void *mmr_base; member in struct:mbcs_soft
/drivers/dma/
H A Dmv_xor.h50 #define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
51 #define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
52 #define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30)
53 #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
54 #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50)
55 #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
92 * @mmr_base: memory mapped register base
106 void __iomem *mmr_base; member in struct:mv_xor_chan

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