Searched defs:mode (Results 176 - 200 of 403) sorted by relevance

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/arch/arm/mach-at91/include/mach/
H A Dat91sam9_smc.h40 u32 mode; member in struct:sam9_smc_config
/arch/arm/mach-cns3xxx/
H A Dcore.c116 static void cns3xxx_timer_set_mode(enum clock_event_mode mode, argument
123 switch (mode) {
/arch/arm/mach-davinci/
H A Ddevices.c311 void davinci_restart(enum reboot_mode mode, const char *cmd) argument
/arch/arm/mach-ebsa110/
H A Dcore.c221 * Timer 1, mode 2, LSB/MSB
314 static void ebsa110_restart(enum reboot_mode mode, const char *cmd) argument
/arch/arm/mach-imx/
H A Depit.c109 static void epit_set_mode(enum clock_event_mode mode, argument
123 if (mode != clockevent_mode) {
130 /* Remember timer mode */
131 clockevent_mode = mode;
134 switch (mode) {
136 printk(KERN_ERR "epit_set_mode: Periodic mode is not "
144 * mode switching
H A Dpm-imx5.c77 * set cpu low power mode before WFI instruction. This function is called
80 static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) argument
86 /* always allow platform to issue a deep sleep mode request */
98 switch (mode) {
108 if (mode == WAIT_UNCLOCKED_POWER_OFF) {
126 printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
H A Dtime.c64 #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
190 static void mxc_set_mode(enum clock_event_mode mode, argument
204 if (mode != clockevent_mode) {
218 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
220 clock_event_mode_label[mode]);
223 /* Remember timer mode */
224 clockevent_mode = mode;
227 switch (mode) {
229 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
237 * mode switchin
[all...]
/arch/arm/mach-iop13xx/
H A Dsetup.c599 void iop13xx_restart(enum reboot_mode mode, const char *cmd) argument
/arch/arm/mach-msm/
H A Dsmd_debug.c212 static void debug_create(const char *name, umode_t mode, argument
216 debugfs_create_file(name, mode, dent, fill, &debug_ops);
/arch/arm/mach-mv78xx0/
H A Dcommon.c416 void mv78xx0_restart(enum reboot_mode mode, const char *cmd) argument
/arch/arm/mach-nomadik/
H A Dcpu-8815.c102 static void cpu8815_restart(enum reboot_mode mode, const char *cmd) argument
/arch/arm/mach-omap2/
H A Dcm33xx.c38 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
154 * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
159 * is in hardware-supervised idle mode, or 0 otherwise.
173 * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
178 * hardware-supervised idle mode. No return value.
186 * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
191 * software-supervised idle mode, i.e., controlled manually by the
277 * @mode: Module mode (SW or HW)
284 void am33xx_cm_module_enable(u8 mode, u1 argument
[all...]
H A Dcminst44xx.c49 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
195 * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
201 * is in hardware-supervised idle mode, or 0 otherwise.
215 * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
221 * hardware-supervised idle mode. No return value.
229 * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
235 * software-supervised idle mode, i.e., controlled manually by the
320 * @mode: Module mode (SW or HW)
328 void omap4_cminst_module_enable(u8 mode, u argument
[all...]
/arch/arm/mach-pxa/
H A Dpxa27x.c254 int __init pxa27x_set_pwrmode(unsigned int mode) argument
256 switch (mode) {
259 pwrmode = mode;
/arch/arm/mach-realview/
H A Drealview_eb.c330 /* new irq mode */
422 static void realview_eb_restart(enum reboot_mode mode, const char *cmd) argument
H A Drealview_pb1176.c334 static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd) argument
H A Drealview_pb11mp.c275 /* new irq mode with no DCC */
320 static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd) argument
H A Drealview_pba8.c268 static void realview_pba8_restart(enum reboot_mode mode, const char *cmd) argument
H A Drealview_pbx.c345 static void realview_pbx_restart(enum reboot_mode mode, const char *cmd) argument
/arch/arm/mach-s3c64xx/
H A Dcommon.c435 void s3c64xx_restart(enum reboot_mode mode, const char *cmd) argument
437 if (mode != REBOOT_SOFT)
440 /* if all else fails, or mode was for soft, jump to 0 */
/arch/arm/mach-sa1100/
H A Dgeneric.c88 /* enter sleep mode */
92 void sa11x0_restart(enum reboot_mode mode, const char *cmd) argument
94 if (mode == REBOOT_SOFT) {
/arch/arm/mach-shmobile/
H A Dclock-r8a7779.c210 u32 mode = r8a7779_read_mode_pins(); local
213 if (mode & MD(1)) {
225 if (mode & MD(2)) {
244 if (mode & MD(2)) {
/arch/arm/mach-spear/
H A Dtime.c69 static void clockevent_set_mode(enum clock_event_mode mode,
89 val &= ~CTRL_ONE_SHOT; /* autoreload mode */
106 static void clockevent_set_mode(enum clock_event_mode mode, argument
117 switch (mode) {
141 pr_err("Invalid mode requested\n");
/arch/arm64/kvm/
H A Dguest.c100 u32 mode = (*(u32 *)valp) & COMPAT_PSR_MODE_MASK; local
101 switch (mode) {
/arch/avr32/kernel/
H A Dprocess.c41 * Enter Stop mode. The 32 kHz oscillator will keep running so
216 unsigned long mode = (regs->sr & MODE_MASK) >> MODE_SHIFT; local
256 printk("%sCPU Mode: %s\n", log_lvl, cpu_modes[mode]);

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