Searched defs:mode_offset (Results 1 - 4 of 4) sorted by relevance
/drivers/gpu/drm/qxl/ |
H A D | qxl_kms.c | 45 int mode_offset; local 66 mode_offset = rom->modes_offset / 4; 67 qdev->mode_info.num_modes = ((u32 *)rom)[mode_offset]; 70 qdev->mode_info.modes = (void *)((uint32_t *)rom + mode_offset + 1);
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/drivers/clk/rockchip/ |
H A D | clk-pll.c | 283 int lock_shift, int mode_offset, int mode_shift, 373 pll_mux->reg = base + mode_offset; 280 rockchip_clk_register_pll(enum rockchip_pll_type pll_type, const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, spinlock_t *lock) argument
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H A D | clk.h | 80 * @mode_offset: offset of the register for configuring the PLL-mode. 93 int mode_offset; member in struct:rockchip_pll_clock 110 .mode_offset = _mode, \
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/drivers/net/wireless/ath/ath5k/ |
H A D | eeprom.c | 470 u32 mode_offset[3]; local 478 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version); 479 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version); 480 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version); 486 offset = mode_offset[mode];
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