Searched defs:mscr (Results 1 - 3 of 3) sorted by relevance
/drivers/net/phy/ |
H A D | marvell.c | 305 int err, oldpage, mscr; local 319 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) & 323 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY | 326 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY; 328 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY; 330 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr); 359 int err, oldpage, mscr; local 368 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG); 369 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD; 371 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr); [all...] |
/drivers/net/ethernet/dlink/ |
H A D | dl2k.c | 1403 __u16 mscr; local 1419 mscr = mii_read (dev, phy_addr, MII_CTRL1000); 1421 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) { 1425 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) { 1563 mscr = mii_read (dev, phy_addr, MII_CTRL1000); 1564 mscr |= MII_MSCR_CFG_ENABLE; 1565 mscr &= ~MII_MSCR_CFG_VALUE = 0;
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/drivers/edac/ |
H A D | cpc925_edac.c | 896 u32 mscr; local 899 mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET); 900 si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT; 902 edac_dbg(0, "Mem Scrub Ctrl Register 0x%x\n", mscr); 904 if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) ||
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