/drivers/net/ethernet/atheros/alx/ |
H A D | hw.c | 62 u16 reg, u16 *phy_data) 67 *phy_data = 0; 94 *phy_data = ALX_GET_FIELD(val, ALX_MDIO_DATA); 99 u16 reg, u16 phy_data) 115 phy_data << ALX_MDIO_DATA_SHIFT | 121 phy_data << ALX_MDIO_DATA_SHIFT | 129 static int __alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data) argument 131 return alx_read_phy_core(hw, false, 0, reg, phy_data); 134 static int __alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data) argument 136 return alx_write_phy_core(hw, false, 0, reg, phy_data); 61 alx_read_phy_core(struct alx_hw *hw, bool ext, u8 dev, u16 reg, u16 *phy_data) argument 98 alx_write_phy_core(struct alx_hw *hw, bool ext, u8 dev, u16 reg, u16 phy_data) argument 171 alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data) argument 182 alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data) argument [all...] |
/drivers/net/ethernet/atheros/atl1c/ |
H A D | atl1c_ethtool.c | 140 u16 phy_data; local 168 atl1c_read_phy_reg(hw, MII_BMCR, &phy_data); 169 regs_buff[AT_REGS_LEN/sizeof(u32) - 2] = (u32) phy_data; 170 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); 171 regs_buff[AT_REGS_LEN/sizeof(u32) - 1] = (u32) phy_data;
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H A D | atl1c_hw.c | 88 u16 phy_data; local 109 atl1c_read_phy_dbg(hw, MIIDBG_ANACTRL, &phy_data); 110 phy_data &= ~ANACTRL_HB_EN; 111 atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, phy_data); 112 atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data); 113 phy_data |= VOLT_CTRL_SWLOWEST; 114 atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data); 138 atl1c_read_phy_dbg(hw, MIIDBG_ANACTRL, &phy_data); 139 phy_data |= ANACTRL_HB_EN; 140 atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, phy_data); 315 atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, u16 reg, u16 *phy_data) argument 364 atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, u16 reg, u16 phy_data) argument 408 atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data) argument 419 atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data) argument 425 atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr, u16 reg_addr, u16 *phy_data) argument 432 atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr, u16 reg_addr, u16 phy_data) argument 438 atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data) argument 451 atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data) argument 514 u16 phy_data; local 662 u16 phy_data; local 702 u16 phy_data; local 773 u16 phy_data; local [all...] |
H A D | atl1c_main.c | 255 u16 speed, duplex, phy_data; local 259 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); 260 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); 263 if ((phy_data & BMSR_LSTATUS) == 0) { 307 u16 phy_data; local 311 atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 312 atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 314 link_up = phy_data & BMSR_LSTATUS; 1538 u16 phy_data; local 1541 atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data); [all...] |
/drivers/net/ethernet/atheros/atl1e/ |
H A D | atl1e_ethtool.c | 155 u16 phy_data; local 192 atl1e_read_phy_reg(hw, MII_BMCR, &phy_data); 193 regs_buff[73] = (u32)phy_data; 194 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data); 195 regs_buff[74] = (u32)phy_data;
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H A D | atl1e_hw.c | 213 int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data) argument 234 *phy_data = (u16)val; 247 int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data) argument 252 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 391 u16 phy_data; local 393 phy_data = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART; 395 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data); 599 u16 phy_data; local 602 err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data); 606 if (!(phy_data [all...] |
H A D | atl1e_main.c | 168 u16 speed, duplex, phy_data; local 171 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data); 172 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data); 173 if ((phy_data & BMSR_LSTATUS) == 0) { 231 u16 phy_data = 0; local 235 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 236 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 238 link_up = phy_data & BMSR_LSTATUS; 1239 u16 phy_data; local 1242 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data); [all...] |
/drivers/net/ethernet/atheros/atlx/ |
H A D | atl1.c | 359 static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data) argument 377 *phy_data = (u16) val; 606 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data) argument 611 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 657 u16 phy_data; local 661 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; 665 phy_data = 670 phy_data = MII_CR_SPEED_100 | MII_CR_RESET; 673 phy_data = 678 phy_data 889 u16 phy_data; local 1304 u16 speed, duplex, phy_data; local 3277 u16 phy_data; local 3639 u16 phy_data; local [all...] |
H A D | atl2.c | 570 u16 phy_data = 0; local 573 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 574 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 578 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ 592 u16 phy_data; local 594 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); 1173 u16 speed, duplex, phy_data; local 1177 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1178 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1179 if (!(phy_data 1860 u16 phy_data; local 2477 u16 phy_data; local 2511 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) argument 2546 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) argument 2656 u16 phy_data; local [all...] |
H A D | atlx.c | 44 static s32 atlx_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data); 95 u16 phy_data = 0; local 99 atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 100 atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 104 if (!(phy_data & BMSR_LSTATUS)) { 187 u16 phy_data; local 191 atlx_read_phy_reg(&adapter->hw, 19, &phy_data);
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/drivers/net/ethernet/dec/tulip/ |
H A D | dmfe.c | 1791 u16 phy_data, u32 chip_id) 1796 dw16(0x80 + offset * 4, phy_data); 1829 phy_data & i ? PHY_DATA_1 : PHY_DATA_0); 1841 u16 phy_data; local 1845 phy_data = dr16(0x80 + offset * 4); 1875 for (phy_data = 0, i = 0; i < 16; i++) { 1876 phy_data <<= 1; 1877 phy_data |= dmfe_phy_read_1bit(ioaddr); 1881 return phy_data; 1889 static void dmfe_phy_write_1bit(void __iomem *ioaddr, u32 phy_data) argument 1790 dmfe_phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id) argument 1906 u16 phy_data; local [all...] |
H A D | uli526x.c | 1636 u8 offset, u16 phy_data) 1666 phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0); 1671 u16 phy_data; local 1698 for (phy_data = 0, i = 0; i < 16; i++) { 1699 phy_data <<= 1; 1700 phy_data |= phy_read_1bit(db); 1703 return phy_data; 1725 u8 offset, u16 phy_data) 1731 cr10_value = (cr10_value << 16) + 0x04000000 + phy_data; 1759 u16 phy_data; local 1635 phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset, u16 phy_data) argument 1724 phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr, u8 offset, u16 phy_data) argument [all...] |
/drivers/net/ethernet/intel/e1000/ |
H A D | e1000_ethtool.c | 350 u16 phy_data; local 376 IGP01E1000_PHY_PAGE_SELECT, &phy_data); 377 regs_buff[13] = (u32)phy_data; /* cable length */ 381 IGP01E1000_PHY_PAGE_SELECT, &phy_data); 382 regs_buff[14] = (u32)phy_data; /* cable length */ 386 IGP01E1000_PHY_PAGE_SELECT, &phy_data); 387 regs_buff[15] = (u32)phy_data; /* cable length */ 391 IGP01E1000_PHY_PAGE_SELECT, &phy_data); 392 regs_buff[16] = (u32)phy_data; /* cable length */ 396 IGP01E1000_PHY_PAGE_SELECT, &phy_data); [all...] |
H A D | e1000_hw.c | 78 u16 phy_data); 80 u16 *phy_data); 1033 u16 phy_data; local 1069 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1070 phy_data |= 0x00000008; 1072 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1092 u16 phy_data; local 1122 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1129 phy_data &= 1136 phy_data 1232 u16 phy_data; local 1338 u16 phy_data; local 1446 u16 phy_data; local 1675 u16 phy_data; local 1935 u16 phy_data; local 2406 u16 phy_data; local 2587 u16 phy_data; local 2652 u16 phy_data; local 2815 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) argument 2839 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) argument 2953 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) argument 2977 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) argument 3131 u16 phy_data; local 3269 u16 phy_data, min_length, max_length, average; local 3348 u16 phy_data; local 3420 u16 phy_data; local 4926 u16 i, phy_data; local 5041 u16 phy_data; local 5107 u16 phy_data; local 5140 u16 phy_data, i; local 5217 u16 phy_data, phy_saved_data, speed, duplex, i; local 5397 u16 phy_data; local 5500 u16 phy_data; local [all...] |
/drivers/net/ethernet/intel/e1000e/ |
H A D | 80003es2lan.c | 542 u16 phy_data; local 548 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 552 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 553 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); 557 e_dbg("GG82563 PSCR: %X\n", phy_data); 559 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); 563 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 566 phy_data |= BMCR_RESET; 568 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); 598 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 631 u16 phy_data, index; local [all...] |
H A D | ethtool.c | 436 u16 phy_data; local 466 e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 467 regs_buff[13] = (u32)phy_data; /* cable length */ 471 e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 472 regs_buff[17] = (u32)phy_data; /* extended 10bt distance */ 481 e1e_rphy(hw, MII_STAT1000, &phy_data); 482 regs_buff[24] = (u32)phy_data; /* phy local receiver status */ 2136 u16 cap_addr, lpa_addr, pcs_stat_addr, phy_data; local 2166 ret_val = e1000_read_emi_reg_locked(hw, cap_addr, &phy_data); 2169 edata->supported = mmd_eee_cap_to_ethtool_sup_t(phy_data); [all...] |
H A D | ich8lan.c | 1866 u16 phy_data; local 1874 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 1878 phy_data &= ~HV_SMB_ADDR_MASK; 1879 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 1880 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 1885 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 1886 phy_data |= (freq & (1 << 0)) << 1888 phy_data |= (freq & (1 << 1)) << 1895 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2241 u16 phy_data; local 4965 u16 phy_data; local [all...] |
H A D | netdev.c | 3072 u16 phy_data; local 3074 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3075 phy_data &= 0xfff8; 3076 phy_data |= (1 << 2); 3077 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3079 e1e_rphy(hw, 22, &phy_data); 3080 phy_data &= 0x0fff; 3081 phy_data |= (1 << 14); 3084 e1e_wphy(hw, 22, phy_data); 3989 u16 phy_data local 4594 u16 phy_data; local 6288 u16 phy_data; local [all...] |
H A D | phy.c | 606 u16 phy_data; local 609 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data); 614 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ? 615 ((phy_data & CTL1000_AS_MASTER) ? 620 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 623 phy_data |= CTL1000_ENABLE_MASTER; 624 phy_data &= ~(CTL1000_AS_MASTER); 627 phy_data &= ~CTL1000_ENABLE_MASTER; 633 return e1e_wphy(hw, MII_CTRL1000, phy_data); 645 u16 phy_data; local 700 u16 phy_data; local 1203 u16 phy_data; local 1267 u16 phy_data; local 1572 u16 phy_data, offset, mask; local 1679 u16 phy_data, offset, mask; local 1798 u16 phy_data, index; local 1833 u16 phy_data, i, agc_value = 0; local 1901 u16 phy_data; local 3116 u16 phy_data; local 3222 u16 phy_data, length; local [all...] |
/drivers/net/ethernet/intel/igb/ |
H A D | e1000_82575.c | 2617 u16 phy_data; local 2630 &phy_data); 2634 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 2636 phy_data); 2648 &phy_data); 2653 phy_data |= E1000_EEE_ADV_100_SUPPORTED; 2655 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED; 2658 phy_data |= E1000_EEE_ADV_1000_SUPPORTED; 2660 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED; 2664 phy_data); 2696 u16 phy_data; local [all...] |
H A D | e1000_phy.c | 481 u16 phy_data; local 497 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); 501 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; 504 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; 506 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); 511 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 514 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 524 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX; 528 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX; 531 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 548 u16 phy_data; local 652 u16 phy_data; local 1156 u16 phy_data; local 1221 u16 phy_data; local 1498 u16 phy_data, offset, mask; local 1695 u16 phy_data, index; local 1721 u16 phy_data, phy_data2, index, default_page, is_cm; local 1841 u16 phy_data, i, agc_value = 0; local 1912 u16 phy_data; local 2269 u16 phy_data; local 2395 u16 phy_data, length; local 2482 u16 phy_data; local [all...] |
H A D | igb_ethtool.c | 2599 u16 phy_data; local 2631 &phy_data); 2635 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 2642 &phy_data); 2646 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
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/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_phy.c | 237 * @phy_data: Pointer to read data from PHY register 240 u16 *phy_data) 302 *phy_data = (u16)(data); 312 * @phy_data: Pointer to read data from PHY register 315 u32 device_type, u16 *phy_data) 327 phy_data); 342 * @phy_data: Data to write to the PHY register 345 u32 device_type, u16 phy_data) 350 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 415 * @phy_data 239 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data) argument 314 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data) argument 344 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data) argument 417 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data) argument 597 u16 phy_data = 0; local 748 u16 phy_data = 0; local 1943 u16 phy_data = 0; local [all...] |
/drivers/net/ethernet/ |
H A D | jme.c | 1761 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data) argument 1767 phy_data); 1775 u32 ctrl1000, phy_data; local 1785 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG); 1786 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0; 1787 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH | 1789 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data); 1791 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG); 1792 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE | 1795 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data); [all...] |
H A D | lantiq_etop.c | 339 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) argument 344 phy_data;
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