Searched defs:pll_rate (Results 1 - 4 of 4) sorted by relevance

/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8960.c46 struct pll_rate { struct
55 static const struct pll_rate freqtbl[] = {
323 static const struct pll_rate *find_rate(unsigned long rate)
342 const struct pll_rate *pll_rate = find_rate(rate); local
343 return pll_rate->rate;
351 const struct pll_rate *pll_rate = find_rate(rate); local
356 for (i = 0; pll_rate->conf[i].reg; i++)
357 hdmi_write(hdmi, pll_rate
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/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4_lvds_pll.c36 struct pll_rate { struct
45 static const struct pll_rate freqtbl[] = {
59 static const struct pll_rate *find_rate(unsigned long rate)
72 const struct pll_rate *pll_rate = find_rate(lvds_pll->pixclk); local
75 DBG("pixclk=%lu (%lu)", lvds_pll->pixclk, pll_rate->rate);
77 if (WARN_ON(!pll_rate))
82 for (i = 0; pll_rate->conf[i].reg; i++)
83 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate
115 const struct pll_rate *pll_rate = find_rate(rate); local
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/drivers/clk/spear/
H A Dclk-vco-pll.c31 * pll_rate = pll/2^p
70 unsigned long prate, int index, unsigned long *pll_rate)
78 if (pll_rate)
79 *pll_rate = (rate / (1 << rtbl[index].p)) * 10000;
69 pll_calc_rate(struct pll_rate_tbl *rtbl, unsigned long prate, int index, unsigned long *pll_rate) argument
/drivers/mfd/
H A Ddb8500-prcmu.c1501 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, function
1557 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1559 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1561 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1589 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1601 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1626 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1651 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1653 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1657 return pll_rate(PRCM_PLLDDR_FRE
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