Searched defs:priority (Results 1 - 25 of 28) sorted by relevance

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/arch/arm/mach-at91/
H A Dat91x40.c61 * The default interrupt priority levels (0 = lowest, 7 = highest).
85 void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS]) argument
89 if (!priority)
90 priority = at91x40_default_irq_priority;
92 at91_aic_init(priority, extern_irq);
H A Dirq.c250 void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask) argument
289 /* Active Low interrupt, with the specified priority */
290 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); local
H A Dsetup.c50 void __init at91_init_interrupts(unsigned int *priority) argument
54 at91_aic_init(priority, at91_boot_soc.extern_irq);
/arch/sh/include/asm/
H A Dhw_irq.h14 unsigned char priority; /* The priority */ member in struct:ipr_data
/arch/mips/kvm/
H A Dinterrupt.c25 void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, uint32_t priority) argument
27 set_bit(priority, &vcpu->arch.pending_exceptions);
30 void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, uint32_t priority) argument
32 clear_bit(priority, &vcpu->arch.pending_exceptions);
115 /* Deliver the interrupt of the corresponding priority, if possible. */
116 int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority, argument
125 switch (priority) {
192 clear_bit(priority, &vcpu->arch.pending_exceptions);
198 int kvm_mips_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority, argument
208 unsigned int priority; local
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/arch/arm/mach-omap1/
H A Dirq.c125 * Allows tuning the IRQ type and priority
131 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) argument
139 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
/arch/mips/cavium-octeon/executive/
H A Dcvmx-pko.c51 uint64_t priority = 8; local
67 &priority);
193 * @priority: Array of priority levels for each queue. Values are
197 * on the fly while the pko is enabled. A priority of 9
198 * indicates that static priority should be used. If static
199 * priority is used all queues with static priority must be
201 * queues have higher priority than higher numbered queues.
206 const uint64_t priority[])
204 cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint64_t num_queues, const uint64_t priority[]) argument
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/arch/mips/pnx833x/common/
H A Dinterrupts.c109 unsigned long priority = PNX833X_PIC_INT_PRIORITY; local
124 PNX833X_PIC_INT_PRIORITY = priority;
144 /* Currently we do this by setting IRQ priority to 1.
145 If priority support is being implemented, 1 should be repalced
152 /* Disable IRQ by writing setting it's priority to 0 */
271 /* Set PIC priority limiter register to 0 */
/arch/powerpc/kvm/
H A Dbook3s_rtas.c23 u32 irq, server, priority; local
33 priority = be32_to_cpu(args->args[2]);
35 rc = kvmppc_xics_set_xive(vcpu->kvm, irq, server, priority);
44 u32 irq, server, priority; local
54 server = priority = 0;
55 rc = kvmppc_xics_get_xive(vcpu->kvm, irq, &server, &priority);
62 args->rets[2] = cpu_to_be32(priority);
H A Dbook3s_xics.h38 u8 priority; member in struct:ics_irq_state
H A Dbook3s_xics.c121 state->priority);
133 u32 server, u32 priority, u32 saved_priority)
140 state->priority = priority;
143 if ((state->masked_pending || state->resend) && priority != MASKED) {
153 int kvmppc_xics_set_xive(struct kvm *kvm, u32 irq, u32 server, u32 priority) argument
174 irq, server, priority,
177 if (write_xive(xics, ics, state, server, priority, priority))
183 int kvmppc_xics_get_xive(struct kvm *kvm, u32 irq, u32 *server, u32 *priority) argument
131 write_xive(struct kvmppc_xics *xics, struct kvmppc_ics *ics, struct ics_irq_state *state, u32 server, u32 priority, u32 saved_priority) argument
320 icp_try_to_deliver(struct kvmppc_icp *icp, u32 irq, u8 priority, u32 *reject) argument
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H A Dbook3s.c250 int kvmppc_book3s_irqprio_deliver(struct kvm_vcpu *vcpu, unsigned int priority) argument
256 switch (priority) {
313 printk(KERN_ERR "KVM: Unknown interrupt: 0x%x\n", priority);
330 static bool clear_irqprio(struct kvm_vcpu *vcpu, unsigned int priority) argument
332 switch (priority) {
348 unsigned int priority; local
354 priority = __ffs(*pending);
355 while (priority < BOOK3S_IRQPRIO_MAX) {
356 if (kvmppc_book3s_irqprio_deliver(vcpu, priority) &&
357 clear_irqprio(vcpu, priority)) {
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H A Dbooke.c249 unsigned int priority)
251 trace_kvm_booke_queue_irqprio(vcpu, priority);
252 set_bit(priority, &vcpu->arch.pending_exceptions);
376 /* Deliver the interrupt of the corresponding priority, if possible. */
378 unsigned int priority)
401 if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) {
402 priority = BOOKE_IRQPRIO_EXTERNAL;
406 if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags)
409 switch (priority) {
492 vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
248 kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu, unsigned int priority) argument
377 kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu, unsigned int priority) argument
654 unsigned int priority; local
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H A Dmpic.c144 int priority; member in struct:irq_queue
148 uint32_t ivpr; /* IRQ vector/priority register */
181 int32_t ctpr; /* CPU current task priority */
301 int priority = -1; local
309 irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
311 if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
313 priority = IVPR_PRIORITY(opp->src[irq].ivpr);
318 q->priority = priority;
334 int priority; local
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/arch/powerpc/sysdev/xics/
H A Dics-opal.c117 int8_t priority; local
124 rc = opal_get_xive(hw_irq, &oserver, &priority);
145 rc = opal_set_xive(hw_irq, server, priority);
186 int8_t priority; local
192 rc = opal_get_xive(hw_irq, &server, &priority);
206 int8_t priority; local
209 rc = opal_get_xive(vec, &server, &priority);
220 int8_t priority; local
223 rc = opal_get_xive(vec, &server, &priority);
/arch/powerpc/include/asm/
H A Depapr_hcalls.h131 * @priority: interrupt priority
137 uint32_t config, unsigned int priority, uint32_t destination)
148 r5 = priority;
163 * @priority: returned interrupt priority
169 uint32_t *config, unsigned int *priority, uint32_t *destination)
186 *priority = r5;
251 * definition, this is also the highest-priority interrupt.
136 ev_int_set_config(unsigned int interrupt, uint32_t config, unsigned int priority, uint32_t destination) argument
168 ev_int_get_config(unsigned int interrupt, uint32_t *config, unsigned int *priority, uint32_t *destination) argument
/arch/powerpc/sysdev/
H A Dipic.c727 /* default priority scheme is grouped. If spread mode is required
772 int ipic_set_priority(unsigned int virq, unsigned int priority) argument
778 if (priority > 7)
787 if (priority < 4) {
788 temp &= ~(0x7 << (20 + (3 - priority) * 3));
789 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
791 temp &= ~(0x7 << (4 + (7 - priority) * 3));
792 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
/arch/powerpc/sysdev/qe_lib/
H A Dqe_ic.c349 /* default priority scheme is grouped. If spread mode is */
364 /* choose destination signal for highest priority interrupt */
400 int qe_ic_set_priority(unsigned int virq, unsigned int priority) argument
406 if (priority > 8 || priority == 0)
415 if (priority < 4) {
416 temp &= ~(0x7 << (32 - priority * 3));
417 temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
419 temp &= ~(0x7 << (24 - priority * 3));
420 temp |= qe_ic_info[src].pri_code << (24 - priority *
429 qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high) argument
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/arch/x86/kvm/
H A Di8259.c121 * return the highest priority found in mask (highest = smallest
126 int priority; local
129 priority = 0;
130 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
131 priority++;
132 return priority;
140 int mask, cur_priority, priority; local
143 priority = get_priority(s, mask);
144 if (priority == 8)
147 * compute current priority
313 int priority, cmd, irq; local
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/arch/powerpc/platforms/cell/
H A Dinterrupt.c346 * priority of 1. We might want to improve that later.
363 (1 << 12) /* priority */ |
397 void iic_set_interrupt_routing(int cpu, int thread, int priority) argument
404 iic_ir |= CBE_IIC_IR_PRIO(priority) |
/arch/tile/include/hv/
H A Ddrv_mpipe_intf.h527 /** The priority. */
528 int16_t priority; member in struct:__anon2915
/arch/arm/common/
H A Dedma.c290 /* default to low priority queue */
300 int priority)
304 ((priority & 0x7) << bit));
619 * EVENTQ_DEFAULT unless you really need a high priority queue.
1436 /* default to low priority queue */
1475 /* Nothing need to be done if queue priority is provided */
1480 * Configure TC/queue priority as follows:
1481 * Q0 - priority 0
1482 * Q1 - priority 1
1483 * Q2 - priority
299 assign_priority_to_queue(unsigned ctlr, int queue_no, int priority) argument
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/arch/arm/plat-omap/
H A Ddma.c180 void omap_set_dma_priority(int lch, int dst_port, int priority) argument
205 l |= (priority & 0xf) << 8;
212 void omap_set_dma_priority(int lch, int dst_port, int priority) argument
217 if (priority)
727 * @brief omap_dma_set_global_params : Set global priority settings for dma
760 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
763 * @param read_prio - Read priority
764 * @param write_prio - Write priority
/arch/mips/include/asm/octeon/
H A Dcvmx-pow.h1624 * an associated priority value.
1627 * @priority: Vector of 8 priorities, one per POW Input Queue (0-7).
1628 * Highest priority is 0 and lowest is 7. A priority value
1636 const uint8_t priority[])
1643 grp_msk.s.qos0_pri = priority[0];
1644 grp_msk.s.qos1_pri = priority[1];
1645 grp_msk.s.qos2_pri = priority[2];
1646 grp_msk.s.qos3_pri = priority[3];
1647 grp_msk.s.qos4_pri = priority[
1635 cvmx_pow_set_priority(uint64_t core_num, const uint8_t priority[]) argument
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/arch/x86/include/asm/
H A Dapicdef.h209 u32 priority : 8, member in struct:local_apic::__anon3046
216 u32 priority : 8, member in struct:local_apic::__anon3047
223 u32 priority : 8, member in struct:local_apic::__anon3048

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