Searched defs:rate (Results 1 - 25 of 442) sorted by relevance

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/drivers/clk/mxs/
H A Dclk-ssp.c27 void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate) argument
36 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
44 "%s: cannot set clock to %d\n", __func__, rate);
60 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
H A Dclk-pll.c25 * @rate: the clock rate of the pll
27 * The mxs pll is a fixed rate clock with power and gate control,
34 unsigned long rate; member in struct:clk_pll
78 return pll->rate;
90 void __iomem *base, u8 power, unsigned long rate)
107 pll->rate = rate;
89 mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate) argument
H A Dclk.h27 void __iomem *base, u8 power, unsigned long rate);
38 static inline struct clk *mxs_clk_fixed(const char *name, int rate) argument
40 return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
H A Dclk-div.c50 static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate, argument
55 return div->ops->round_rate(&div->divider.hw, rate, prate);
58 static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate, argument
64 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
H A Dclk-frac.c52 static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate, argument
60 if (rate > parent_rate)
63 tmp = rate;
74 static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate, argument
82 if (rate > parent_rate)
85 tmp = rate;
H A Dclk-ref.c27 * clock has a gate control and a fractional * divider. The rate is calculated
28 * as pll rate * (18 / FRAC), where FRAC = 18 ~ 35.
67 static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate, argument
74 tmp = tmp * 18 + rate / 2;
75 do_div(tmp, rate);
90 static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate, argument
99 tmp = tmp * 18 + rate / 2;
100 do_div(tmp, rate);
/drivers/clk/spear/
H A Dclk.c20 unsigned long prev_rate, rate = 0; local
23 prev_rate = rate;
24 rate = calc_rate(hw, parent_rate, *index);
25 if (drate < rate) {
28 rate = prev_rate;
38 return rate;
/drivers/clk/sunxi/
H A Dclk-a10-hosc.c32 u32 rate; local
34 if (of_property_read_u32(node, "clock-frequency", &rate))
37 /* allocate fixed-rate and gate clock structs */
47 /* set up gate and fixed rate properties */
51 fixed->fixed_rate = rate;
/drivers/cpufreq/
H A Dcpufreq_opp.c53 unsigned long rate; local
69 for (i = 0, rate = 0; i < max_opps; i++, rate++) {
70 /* find next rate */
71 opp = dev_pm_opp_find_freq_ceil(dev, &rate);
77 freq_table[i].frequency = rate / 1000;
H A Dat32ap-cpufreq.c54 unsigned int frequency, rate, min_freq; local
73 * AVR32 CPU frequency rate scales in power of two between maximum and
88 rate = clk_round_rate(cpuclk, frequency * 1000) / 1000;
90 if (rate != frequency)
H A Dtegra-cpufreq.c94 unsigned long rate = freq_table[index].frequency; local
102 if (rate >= 816000)
104 else if (rate >= 456000)
113 if (rate == ifreq)
116 ret = clk_set_rate(pll_x_clk, rate * 1000);
119 pr_err("Failed to change pll_x to %lu\n", rate);
/drivers/clk/
H A Dclk-conf.c85 u32 rate; local
87 of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) {
88 if (rate) {
108 rc = clk_set_rate(clk, rate);
110 pr_err("clk: couldn't set %s clock rate: %d\n",
H A Dclk-ls1x.c34 u32 pll, rate; local
37 rate = ((12 + (pll & 0x3f)) * 1000000) +
39 rate *= OSC;
40 rate >>= 1;
42 return rate;
H A Dclk-fixed-factor.c22 * rate - rate is fixed. clk->rate = parent->rate / div * mult
32 unsigned long long int rate; local
34 rate = (unsigned long long int)parent_rate * fix->mult;
35 do_div(rate, fix->div);
36 return (unsigned long)rate;
39 static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, argument
47 best_parent = (rate / fi
55 clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) argument
[all...]
H A Dclk-fixed-rate.c9 * Fixed rate clock implementation
20 * DOC: basic fixed-rate clock that cannot gate
25 * rate - rate is always a fixed value. No clk_set_rate support
50 * clk_register_fixed_rate_with_accuracy - register fixed-rate clock with the
56 * @fixed_rate: non-adjustable clock rate
57 * @fixed_accuracy: non-adjustable clock rate
67 /* allocate fixed-rate clock */
95 * clk_register_fixed_rate - register fixed-rate clock with the clock framework
100 * @fixed_rate: non-adjustable clock rate
119 u32 rate; local
[all...]
/drivers/clk/tegra/
H A Dclk-audio-sync.c28 return sync->rate;
31 static long clk_sync_source_round_rate(struct clk_hw *hw, unsigned long rate, argument
36 if (rate > sync->max_rate)
39 return rate;
42 static int clk_sync_source_set_rate(struct clk_hw *hw, unsigned long rate, argument
47 sync->rate = rate;
58 unsigned long rate, unsigned long max_rate)
70 sync->rate = rate;
57 tegra_clk_register_sync_source(const char *name, unsigned long rate, unsigned long max_rate) argument
[all...]
/drivers/gpu/drm/armada/
H A Darmada_510.c64 uint32_t rate, ref, div; local
66 rate = mode->clock * 1000;
67 ref = clk_round_rate(clk, rate);
68 div = DIV_ROUND_UP(ref, rate);
/drivers/net/wireless/b43legacy/
H A Dmain.h86 int b43legacy_is_cck_rate(int rate) argument
88 return (rate == B43legacy_CCK_RATE_1MB ||
89 rate == B43legacy_CCK_RATE_2MB ||
90 rate == B43legacy_CCK_RATE_5MB ||
91 rate == B43legacy_CCK_RATE_11MB);
95 int b43legacy_is_ofdm_rate(int rate) argument
97 return !b43legacy_is_cck_rate(rate);
/drivers/net/wireless/libertas/
H A Dtx.c22 * @rate: Input rate
25 static u32 convert_radiotap_rate_to_mv(u8 rate) argument
27 switch (rate) {
121 txpd->tx_control = cpu_to_le32(convert_radiotap_rate_to_mv(rtap_hdr->rate));
/drivers/clk/at91/
H A Dclk-h32mx.c52 static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate, argument
57 if (rate > *parent_rate)
60 if (rate < div)
63 if (rate - div < *parent_rate - rate)
69 static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate, argument
76 if (parent_rate != rate && (parent_rate / 2) != rate)
81 if ((parent_rate / 2) == rate)
H A Dclk-plldiv.c39 static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate, argument
44 if (rate > *parent_rate)
47 if (rate < div)
50 if (rate - div < *parent_rate - rate)
56 static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate, argument
63 if (parent_rate != rate && (parent_rate / 2) != rate)
68 if ((parent_rate / 2) == rate)
/drivers/net/wireless/b43/
H A Dmain.h61 static inline int b43_is_cck_rate(int rate) argument
63 return (rate == B43_CCK_RATE_1MB ||
64 rate == B43_CCK_RATE_2MB ||
65 rate == B43_CCK_RATE_5MB || rate == B43_CCK_RATE_11MB);
68 static inline int b43_is_ofdm_rate(int rate) argument
70 return !b43_is_cck_rate(rate);
/drivers/net/wireless/ti/wl18xx/
H A Dtx.c33 u8 band, struct ieee80211_tx_rate *rate)
38 wl1271_error("last Tx rate invalid: %d", fw_rate);
39 rate->idx = 0;
40 rate->flags = 0;
45 rate->idx = fw_rate;
47 rate->idx -= CONF_HW_RATE_INDEX_6MBPS;
48 rate->flags = 0;
50 rate->flags = IEEE80211_TX_RC_MCS;
51 rate->idx = fw_rate - CONF_HW_RATE_INDEX_MCS0;
53 /* SGI modifier is counted as a separate rate */
32 wl18xx_get_last_tx_rate(struct wl1271 *wl, struct ieee80211_vif *vif, u8 band, struct ieee80211_tx_rate *rate) argument
[all...]
/drivers/staging/vt6656/
H A Dint.c74 struct ieee80211_rate *rate; local
93 rate = ieee80211_get_tx_rate(priv->hw, info);
94 tx_rate = rate->hw_value - RATE_18M;
/drivers/clk/mmp/
H A Dclk-frac.c38 unsigned long rate = 0, prev_rate; local
42 prev_rate = rate;
43 rate = (((*prate / 10000) * factor->ftbl[i].den) /
45 if (rate > drate)
49 return rate;
51 if ((drate - prev_rate) > (rate - drate))
52 return rate;
80 /* Configures new clock rate*/
88 unsigned long prev_rate, rate = 0; local
91 prev_rate = rate;
[all...]

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