/arch/arm/mach-s3c64xx/ |
H A D | setup-ide.c | 25 u32 reg; local 27 reg = readl(S3C_MEM_SYS_CFG) & (~0x3f); 30 writel(reg | MEM_SYS_CFG_INDEP_CF |
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/arch/powerpc/lib/ |
H A D | ldstfp.S | 16 #include <asm/reg.h> 31 reg = 0 define 33 20: \op reg,0,r4 36 reg = reg + 1 define 47 reg = 1 define 49 fmr fr0,reg 51 reg = reg + 1 define 66 reg define 70 reg = reg + 1 define 194 reg = 1 define 198 reg = reg + 1 define 213 reg = 1 define 217 reg = reg + 1 define 290 reg = 1 define 294 reg = reg + 1 define 309 reg = 1 define 313 reg = reg + 1 define [all...] |
/arch/x86/boot/ |
H A D | regs.c | 22 void initregs(struct biosregs *reg) argument 24 memset(reg, 0, sizeof *reg); 25 reg->eflags |= X86_EFLAGS_CF; 26 reg->ds = ds(); 27 reg->es = ds(); 28 reg->fs = fs(); 29 reg->gs = gs();
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/arch/arm/mach-imx/ |
H A D | pm-imx3.c | 25 int reg = __raw_readl(mx3_ccm_base + MXC_CCM_CCMR); local 26 reg &= ~MXC_CCM_CCMR_LPM_MASK; 31 reg |= MXC_CCM_CCMR_LPM_WAIT_MX35; 32 __raw_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
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/arch/mips/bcm63xx/ |
H A D | prom.c | 24 u32 reg, mask; local 52 reg = bcm_perf_readl(PERF_CKCTL_REG); 53 reg &= ~mask; 54 bcm_perf_writel(reg, PERF_CKCTL_REG); 70 reg = bcm_readl(BCM_6328_OTP_BASE + 73 if (reg & OTP_6328_REG3_TP1_DISABLED)
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/arch/arm/plat-versatile/ |
H A D | sched-clock.c | 37 void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate) argument 39 ctr = reg;
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/arch/mips/include/asm/dec/ |
H A D | ioasic.h | 24 static inline void ioasic_write(unsigned int reg, u32 v) argument 26 ioasic_base[reg / 4] = v; 29 static inline u32 ioasic_read(unsigned int reg) argument 31 return ioasic_base[reg / 4];
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/arch/arm/mach-ebsa110/ |
H A D | leds.c | 22 u8 reg = __raw_readb(SOFT_BASE); local 25 reg |= 0x80; 27 reg &= ~0x80; 29 __raw_writeb(reg, SOFT_BASE); 34 u8 reg = __raw_readb(SOFT_BASE); local 36 return (reg & 0x80) ? LED_FULL : LED_OFF;
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/arch/arm/mach-omap2/ |
H A D | cm44xx.c | 28 u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg) argument 30 return readl_relaxed(cm_base + inst + reg); 34 void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg) argument 36 writel_relaxed(val, cm_base + inst + reg); 40 u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg) argument 42 return readl_relaxed(cm2_base + inst + reg); 46 void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg) argument 48 writel_relaxed(val, cm2_base + inst + reg);
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/arch/arm/mach-ux500/ |
H A D | cache-l2x0.c | 36 static void ux500_l2c310_write_sec(unsigned long val, unsigned reg) argument
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/arch/arm/plat-samsung/ |
H A D | wakeup-mask.c | 22 void samsung_sync_wakemask(void __iomem *reg, argument 28 val = __raw_readl(reg); 45 printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val); 46 __raw_writel(val, reg);
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/arch/arm64/include/asm/ |
H A D | kvm_mmu.h | 60 * reg: VA to be converted. 62 .macro kern_hyp_va reg 63 and \reg, \reg, #HYP_PAGE_OFFSET_MASK variable
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/arch/mips/include/asm/mach-ralink/ |
H A D | ralink_regs.h | 19 static inline void rt_sysc_w32(u32 val, unsigned reg) argument 21 __raw_writel(val, rt_sysc_membase + reg); 24 static inline u32 rt_sysc_r32(unsigned reg) argument 26 return __raw_readl(rt_sysc_membase + reg); 29 static inline void rt_memc_w32(u32 val, unsigned reg) argument 31 __raw_writel(val, rt_memc_membase + reg); 34 static inline u32 rt_memc_r32(unsigned reg) argument 36 return __raw_readl(rt_memc_membase + reg);
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/arch/mips/lasat/ |
H A D | at93c.h | 9 volatile u32 *reg; member in struct:at93c_defs
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/arch/mips/loongson/common/cs5536/ |
H A D | cs5536_acc.c | 19 void pci_acc_write_reg(int reg, u32 value) argument 23 switch (reg) { 66 u32 pci_acc_read_reg(int reg) argument 71 switch (reg) {
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H A D | cs5536_ehci.c | 19 void pci_ehci_write_reg(int reg, u32 value) argument 23 switch (reg) { 79 u32 pci_ehci_read_reg(int reg) argument 84 switch (reg) {
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H A D | cs5536_ide.c | 19 void pci_ide_write_reg(int reg, u32 value) argument 23 switch (reg) { 100 u32 pci_ide_read_reg(int reg) argument 105 switch (reg) {
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H A D | cs5536_ohci.c | 19 void pci_ohci_write_reg(int reg, u32 value) argument 23 switch (reg) { 74 u32 pci_ohci_read_reg(int reg) argument 79 switch (reg) {
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/arch/x86/include/asm/ |
H A D | processor-cyrix.h | 20 static inline u8 getCx86(u8 reg) argument 22 outb(reg, 0x22); 26 static inline void setCx86(u8 reg, u8 data) argument 28 outb(reg, 0x22); 32 #define getCx86_old(reg) ({ outb((reg), 0x22); inb(0x23); }) 34 #define setCx86_old(reg, data) do { \ 35 outb((reg), 0x22); \
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/arch/x86/xen/ |
H A D | apic.c | 11 static unsigned int xen_io_apic_read(unsigned apic, unsigned reg) argument 17 apic_op.reg = reg; 23 if (reg == 0x1) 25 else if (reg == 0x0)
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/arch/alpha/lib/ |
H A D | fpreg.c | 8 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); 10 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); 14 alpha_read_fp_reg (unsigned long reg) argument 18 switch (reg) { 57 #define LDT(reg,val) asm volatile ("itoft %0,$f"#reg : : "r"(val)); 59 #define LDT(reg,val) asm volatile ("ldt $f"#reg", 63 alpha_write_fp_reg(unsigned long reg, unsigned long val) argument 108 alpha_read_fp_reg_s(unsigned long reg) argument 157 alpha_write_fp_reg_s(unsigned long reg, unsigned long val) argument [all...] |
/arch/arm/mach-at91/ |
H A D | sysirq_mask.c | 57 void __iomem *reg; local 64 reg = base + AT91_RTT_MR; 66 mode = readl_relaxed(reg); 70 writel_relaxed(mode, reg); 71 (void)readl_relaxed(reg); /* flush */
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/arch/arm/mach-orion5x/ |
H A D | board-mss2.c | 72 u32 reg; local 77 reg = readl(RSTOUTn_MASK); 78 reg |= 1 << 2; 79 writel(reg, RSTOUTn_MASK); 81 reg = readl(CPU_SOFT_RESET); 82 reg |= 1; 83 writel(reg, CPU_SOFT_RESET);
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/arch/sh/drivers/pci/ |
H A D | pci-sh7751.c | 82 u32 word, reg; local 97 reg = __raw_readl(SH7751_BCR1); 98 reg |= 0x80000; 99 __raw_writel(reg, SH7751_BCR1);
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/arch/xtensa/platforms/s6105/ |
H A D | setup.c | 36 unsigned long reg; local 38 reg = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL); 39 reg &= ~(S6_GREG1_PLLSEL_GMAC_MASK << S6_GREG1_PLLSEL_GMAC | 41 reg |= S6_GREG1_PLLSEL_GMAC_125MHZ << S6_GREG1_PLLSEL_GMAC | 43 writel(reg, S6_REG_GREG1 + S6_GREG1_PLLSEL); 45 reg = readl(S6_REG_GREG1 + S6_GREG1_CLKGATE); 46 reg &= ~(1 << S6_GREG1_BLOCK_SB); 47 reg &= ~(1 << S6_GREG1_BLOCK_GMAC); 48 writel(reg, S6_REG_GREG1 + S6_GREG1_CLKGATE); 50 reg [all...] |