Searched defs:timing (Results 1 - 25 of 87) sorted by relevance

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/drivers/gpu/drm/tegra/
H A Dmipi-phy.c19 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, argument
22 timing->clkmiss = 0;
23 timing->clkpost = 70 + 52 * period;
24 timing->clkpre = 8;
25 timing->clkprepare = 65;
26 timing->clksettle = 95;
27 timing->clktermen = 0;
28 timing->clktrail = 80;
29 timing->clkzero = 260;
30 timing
52 mipi_dphy_timing_validate(struct mipi_dphy_timing *timing, unsigned long period) argument
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/drivers/gpu/drm/nouveau/core/subdev/bios/
H A Dtiming.c28 #include <subdev/bios/timing.h>
35 u16 timing = 0x0000; local
39 timing = nv_ro16(bios, bit_P.offset + 4);
42 timing = nv_ro16(bios, bit_P.offset + 8);
44 if (timing) {
45 *ver = nv_ro08(bios, timing + 0);
48 *hdr = nv_ro08(bios, timing + 1);
49 *cnt = nv_ro08(bios, timing + 2);
50 *len = nv_ro08(bios, timing + 3);
53 return timing;
75 u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); local
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/drivers/video/fbdev/via/
H A Dvia_modesetting.c33 void via_set_primary_timing(const struct via_display_timing *timing) argument
37 raw.hor_total = timing->hor_total / 8 - 5;
38 raw.hor_addr = timing->hor_addr / 8 - 1;
39 raw.hor_blank_start = timing->hor_blank_start / 8 - 1;
40 raw.hor_blank_end = timing->hor_blank_end / 8 - 1;
41 raw.hor_sync_start = timing->hor_sync_start / 8;
42 raw.hor_sync_end = timing->hor_sync_end / 8;
43 raw.ver_total = timing->ver_total - 2;
44 raw.ver_addr = timing->ver_addr - 1;
45 raw.ver_blank_start = timing
91 via_set_secondary_timing(const struct via_display_timing *timing) argument
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/drivers/cpufreq/
H A Dcris-etraxfs-cpufreq.c80 reg_bif_core_rw_sdram_timing timing = local
82 timing.cpd = (freqs->new == 200000 ? 0 : 1);
86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
/drivers/gpu/drm/rcar-du/
H A Drcar_du_lvdscon.c95 struct display_timing timing; local
97 ret = of_get_display_timing(np, "panel-timing", &timing);
101 videomode_from_timing(&timing, &lvdscon->panel.mode);
/drivers/ide/
H A Dtriflex.c41 u16 timing = 0; local
48 timing = 0x0103;
51 timing = 0x0203;
54 timing = 0x0808;
59 timing = 0x0f0f;
62 timing = 0x0202;
65 timing = 0x0204;
68 timing = 0x0404;
71 timing = 0x0508;
74 timing
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H A Dht6560b.c76 * Perhaps I should explain something about these timing values:
91 * You can obtain optimized timing values by running Holtek IDESETUP.COM
92 * for DOS. DOS drivers get their timing values from command line, where
120 u8 select, timing; local
125 timing = HT_TIMING(drive);
135 if (select != current_select || timing != current_timing) {
137 current_timing = timing;
144 * Set timing for this drive:
146 outb(timing, hwif->io_ports.device_addr);
149 printk("ht6560b: %s: select=%#x timing
285 u8 timing; local
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H A Damd74xx.c47 * amd_set_speed() writes timing values to the chipset registers
51 struct ide_timing *timing)
56 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
60 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
63 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));
66 case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
67 case ATA_UDMA4: t = timing
50 amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask, struct ide_timing *timing) argument
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H A Dqd65xx.c84 static int timings[4]={-1,-1,-1,-1}; /* stores current timing for each timer */
106 * computes the timing value where
147 * tries to find timing from dos driver's table
177 * records the timing
180 static void qd_set_timing (ide_drive_t *drive, u8 timing) argument
185 data |= timing;
188 printk(KERN_DEBUG "%s: %#x\n", drive->name, timing);
/drivers/ata/
H A Dpata_cs5530.c68 /* Now load the right timing register */
76 * cs5530_set_dmamode - DMA timing setup
88 u32 tuning, timing = 0; local
96 timing = 0x00921250;break;
98 timing = 0x00911140;break;
100 timing = 0x00911030;break;
102 timing = 0x00077771;break;
104 timing = 0x00012121;break;
106 timing = 0x00002020;break;
111 timing |
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H A Dpata_triflex.c74 * triflex_load_timing - timing configuration
88 u32 timing = 0; local
100 timing = 0x0103;break;
102 timing = 0x0203;break;
104 timing = 0x0808;break;
108 timing = 0x0F0F;break;
110 timing = 0x0202;break;
112 timing = 0x0204;break;
114 timing = 0x0404;break;
116 timing
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H A Dpata_artop.c33 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
102 const u16 timing[2][5] = { local
107 /* Load the PIO timing active/recovery bits */
108 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
146 * ARTOP6260 and relatives store the timing data differently.
156 const u8 timing[2][5] = { local
161 /* Load the PIO timing active/recovery bits */
162 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
215 /* Load the PIO timing active/recovery bits */
237 * ARTOP6260 and relatives store the timing dat
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H A Dpata_at32.c89 * Setup SMC for the given ATA timing.
96 struct smc_timing timing; local
101 memset(&timing, 0, sizeof(struct smc_timing));
104 timing.read_cycle = ata->cyc8b;
107 timing.nrd_setup = ata->setup;
108 timing.nrd_pulse = ata->act8b;
109 timing.nrd_recover = ata->rec8b;
111 /* Convert nanosecond timing to clock cycles */
112 smc_set_timing(smc, &timing);
152 struct ata_timing timing; local
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H A Dpata_cmd640.c53 struct cmd640_reg *timing = ap->private_data; local
67 /* The second channel has shared timings and the setup timing is
99 /* Load setup timing */
115 timing->reg58[adev->devno] = (t.active << 4) | t.recover;
133 struct cmd640_reg *timing = ap->private_data; local
135 if (ap->port_no != 0 && adev->devno != timing->last) {
136 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]);
137 timing->last = adev->devno;
153 struct cmd640_reg *timing; local
155 timing
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H A Dpata_hpt366.c32 u32 timing; member in struct:hpt_clock
114 * hpt36x_find_mode - find the hpt36x timing
128 return clocks->timing;
238 /* determine timing mask and find matching clock entry */
272 * hpt366_set_dmamode - DMA timing setup
372 /* PCI clocking determines the ATA timing values to use */
H A Dpata_ns87415.c7 * as it requires timing reloads on PIO/DMA transitions but it is otherwise
21 * 8bit shared timing.
56 int timing = 0x44 + 2 * unit; local
63 /* Timing register format is 17 - low nybble read timing with
70 /* Use the same timing for read and write bytes */
72 pci_write_config_word(dev, timing, clocking);
92 /* TODO: Set byte 54 command timing to the best 8bit
H A Dpata_sl82c105.c16 * timing parameters.
67 * sl82c105_configure_piomode - set chip PIO timing
72 * Called to do the PIO mode setup. Our timing registers are shared
84 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); local
86 pci_write_config_word(pdev, timing, pio_timing[pio]);
88 pci_read_config_word(pdev, timing, &dummy);
96 * Called to do the PIO mode setup. Our timing registers are shared
97 * but we want to set the PIO timing by default.
121 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); local
124 pci_write_config_word(pdev, timing, dma_timin
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/drivers/char/
H A Dbfin-otp.c84 * bfin_otp_init_timing - setup OTP timing parameters
90 u32 tp1, tp2, tp3, timing; local
95 timing = tp1 | tp2 | tp3;
96 if (bfrom_OtpCommand(OTP_INIT, timing))
99 return timing;
107 static void bfin_otp_deinit_timing(u32 timing) argument
111 bfrom_OtpCommand(OTP_INIT, timing & ~(-1 << 15));
123 u32 timing, page, base_flags, flags, ret; local
137 timing = bfin_otp_init_timing();
138 if (timing
180 u32 timing; local
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/drivers/pcmcia/
H A Dsa11xx_base.c81 struct soc_pcmcia_timing timing; local
86 soc_common_pcmcia_get_timing(skt, &timing);
88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io);
89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem);
90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr);
144 struct soc_pcmcia_timing timing; local
149 soc_common_pcmcia_get_timing(skt, &timing);
151 p+=sprintf(p, "I/O : %u (%u)\n", timing.io,
154 p+=sprintf(p, "attribute: %u (%u)\n", timing.attr,
157 p+=sprintf(p, "common : %u (%u)\n", timing
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/drivers/video/fbdev/omap2/displays-new/
H A Dpanel-dpi.c208 struct display_timing timing; local
227 r = of_get_display_timing(node, "panel-timing", &timing);
229 dev_err(&pdev->dev, "failed to get video timing\n");
233 videomode_from_timing(&timing, &vm);
/drivers/iio/humidity/
H A Ddht11.c46 /* Data transmission timing (nano seconds) */
70 static unsigned char dht11_decode_byte(int *timing, int threshold) argument
77 if (timing[i] >= threshold)
86 int i, t, timing[DHT11_BITS_PER_READ], threshold, local
111 timing[i] = t / timeres;
114 hum_int = dht11_decode_byte(timing, threshold);
115 hum_dec = dht11_decode_byte(&timing[8], threshold);
116 temp_int = dht11_decode_byte(&timing[16], threshold);
117 temp_dec = dht11_decode_byte(&timing[24], threshold);
118 checksum = dht11_decode_byte(&timing[3
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/drivers/iio/light/
H A Dtcs3414.c59 u8 timing; member in struct:tcs3414_data
158 *val2 = tcs3414_times[data->timing & TCS3414_INTEG_MASK] * 1000;
189 data->timing &= ~TCS3414_INTEG_MASK;
190 data->timing |= i;
193 data->timing);
321 data->timing = TCS3414_INTEG_12MS; /* free running */
323 data->timing);
/drivers/media/i2c/
H A Dbt819.c73 struct timing { struct
83 static struct timing timing_data[] = {
188 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; local
191 (((timing->vdelay >> 8) & 0x03) << 6) |
192 (((timing->vactive >> 8) & 0x03) << 4) |
193 (((timing->hdelay >> 8) & 0x03) << 2) |
194 ((timing->hactive >> 8) & 0x03);
195 init[0x04 * 2 - 1] = timing->vdelay & 0xff;
196 init[0x05 * 2 - 1] = timing
251 struct timing *timing = NULL; local
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/drivers/mmc/core/
H A Dsdio.c475 unsigned int bus_speed, timing; local
487 timing = MMC_TIMING_UHS_SDR12;
491 timing = MMC_TIMING_UHS_SDR104;
497 timing = MMC_TIMING_UHS_DDR50;
504 timing = MMC_TIMING_UHS_SDR50;
511 timing = MMC_TIMING_UHS_SDR25;
519 timing = MMC_TIMING_UHS_SDR12;
535 mmc_set_timing(card->host, timing);
/drivers/net/can/
H A Dbfin_can.c44 * bfin can timing parameters
56 * apply to the bit timing configuration when BRP is less than 4.
68 u16 clk, timing; local
71 timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) |
79 timing |= SAM;
82 bfin_write(&reg->timing, timing);
84 netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing);

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