Searched defs:v_offset (Results 1 - 4 of 4) sorted by last modified time
/drivers/gpu/drm/radeon/ |
H A D | radeon_legacy_tv.c | 430 int v_offset, h_offset; local 493 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); 495 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); 497 restart -= v_offset + h_offset;
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/drivers/gpu/drm/tegra/ |
H A D | dc.c | 144 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; local 171 v_offset = window->src.y; 212 v_offset += window->src.h - 1; 215 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); 439 unsigned int h_offset = 0, v_offset = 0; local 506 v_offset += fb->height - 1; 514 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
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/drivers/gpu/ipu-v3/ |
H A D | ipu-cpmem.c | 399 int u_offset, int v_offset) 406 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8); 410 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8); 426 int u_offset, v_offset; local 434 v_offset = u_offset + (uv_stride * height / 2); 436 u_offset, v_offset); 441 v_offset = u_offset + (uv_stride * height); 443 u_offset, v_offset); 595 int offset, u_offset, v_offset; local 612 v_offset 397 ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, u32 pixel_format, int stride, int u_offset, int v_offset) argument [all...] |
/drivers/dma/ipu/ |
H A D | ipu_idmac.c | 277 u32 u_offset, u32 v_offset) 281 params->pp.vbo_l = v_offset & 0x1ffff; 282 params->pp.vbo_h = v_offset >> 17; 290 u32 v_offset; local 395 v_offset = u_offset + u_offset / 4; 396 ipu_ch_param_set_plane_offset(params, u_offset, v_offset); 403 v_offset = stride * height; 404 u_offset = v_offset + v_offset / 2; 405 ipu_ch_param_set_plane_offset(params, u_offset, v_offset); 276 ipu_ch_param_set_plane_offset(union chan_param_mem *params, u32 u_offset, u32 v_offset) argument [all...] |
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