Searched defs:value (Results 1 - 25 of 1989) sorted by relevance

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/drivers/acpi/acpica/
H A Dhwacpi.c151 u32 value; local
169 status = acpi_read_bit_register(ACPI_BITREG_SCI_ENABLE, &value);
174 if (value) {
H A Devxfevnt.c179 u32 value; local
204 enable_register_id, &value);
209 if (value != 1) {
236 u32 value; local
259 enable_register_id, &value);
264 if (value != 0) {
H A Dexoparg2.c59 * and whether or not a value is returned:
69 * zR - RETURN VALUE: Indicates whether this opcode type returns a value
84 * value.
93 u32 value; local
108 /* Second value is the notify value */
110 value = (u32) operand[1]->integer.value;
130 status = acpi_ev_queue_notify_request(node, value);
152 * and one implicit return value
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H A Dhwvalid.c209 * Value Where value is placed
212 * RETURN: Status and value read from port
220 acpi_status acpi_hw_read_port(acpi_io_address address, u32 *value, u32 width) argument
236 status = acpi_os_read_port(address, value, width);
249 for (i = 0, *value = 0; i < width; i += 8) {
259 *value |= (one_byte << i);
284 acpi_status acpi_hw_write_port(acpi_io_address address, u32 value, u32 width) argument
299 status = acpi_os_write_port(address, value, width);
318 acpi_os_write_port(address, (value >> i) & 0xFF, 8);
H A Dhwxface.c90 * hardcode it here and ignore the FADT value. This maintains
99 /* Write the reset value to the reset register */
113 * PARAMETERS: value - Where the value is returned
187 /* Set the return value only if status is AE_OK */
207 * PARAMETERS: value - Value to be written
215 acpi_status acpi_write(u64 value, struct acpi_generic_address *reg)
236 address, value, reg->bit_width);
248 address, ACPI_LODWORD(value),
257 ACPI_HIDWORD(value), 3
304 u32 value; local
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/drivers/gpu/drm/nouveau/core/core/
H A Denum.c32 nouveau_enum_find(const struct nouveau_enum *en, u32 value) argument
35 if (en->value == value)
44 nouveau_enum_print(const struct nouveau_enum *en, u32 value) argument
46 en = nouveau_enum_find(en, value);
50 pr_cont("(unknown enum 0x%08x)", value);
55 nouveau_bitfield_print(const struct nouveau_bitfield *bf, u32 value) argument
58 if (value & bf->mask) {
60 value &= ~bf->mask;
66 if (value)
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H A Doption.c55 nouveau_boolopt(const char *optstr, const char *opt, bool value) argument
65 value = false;
71 value = true;
74 return value;
/drivers/hid/
H A Dhid-xinmo.c29 struct hid_usage *usage, __s32 value)
36 if (value < -1) {
28 xinmo_event(struct hid_device *hdev, struct hid_field *field, struct hid_usage *usage, __s32 value) argument
/drivers/md/persistent-data/
H A Ddm-array.h19 * The value type structure is reused from the btree type to support proper
51 * d) Get a value from the array with dm_array_get_value().
53 * e) Set a value in the array with dm_array_set_value().
102 * value - if we're growing the array the new entries will have this value
105 * If growing the inc function for 'value' will be called the appropriate
111 const void *value, dm_block_t *new_root)
112 __dm_written_to_disk(value); variable
121 * Lookup a value in the array
126 * value
150 __dm_written_to_disk(value); variable
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/drivers/media/usb/cx231xx/
H A Dcx231xx-dif.h29 u32 value; member in struct:dif_settings
/drivers/platform/x86/
H A Dintel-smartconnect.c28 unsigned long long value; local
31 status = acpi_evaluate_integer(acpi->handle, "GAOS", NULL, &value);
35 if (value & 0x1) {
/drivers/usb/dwc3/
H A Dio.h30 u32 value; local
37 value = readl(base + offs);
44 dwc3_trace(trace_dwc3_readl, "addr %p value %08x",
45 base - DWC3_GLOBALS_REGS_START + offset, value);
47 return value;
50 static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) argument
59 writel(value, base + offs);
66 dwc3_trace(trace_dwc3_writel, "addr %p value %08x",
67 base - DWC3_GLOBALS_REGS_START + offset, value);
/drivers/base/regmap/
H A Dregcache-flat.c46 unsigned int reg, unsigned int *value)
50 *value = cache[reg];
56 unsigned int value)
60 cache[reg] = value;
45 regcache_flat_read(struct regmap *map, unsigned int reg, unsigned int *value) argument
55 regcache_flat_write(struct regmap *map, unsigned int reg, unsigned int value) argument
/drivers/gpu/drm/nouveau/core/include/core/
H A Denum.h5 u32 value; member in struct:nouveau_enum
12 nouveau_enum_find(const struct nouveau_enum *, u32 value);
15 nouveau_enum_print(const struct nouveau_enum *en, u32 value);
22 void nouveau_bitfield_print(const struct nouveau_bitfield *, u32 value);
/drivers/leds/
H A Dleds.h21 enum led_brightness value)
23 if (value > led_cdev->max_brightness)
24 value = led_cdev->max_brightness;
25 led_cdev->brightness = value;
27 led_cdev->brightness_set(led_cdev, value);
20 __led_set_brightness(struct led_classdev *led_cdev, enum led_brightness value) argument
/drivers/media/dvb-core/
H A Ddvb_math.c63 unsigned int intlog2(u32 value) argument
66 * returns: log2(value) * 2^24
67 * wrong result if value = 0 (log2(0) is undefined)
74 if (unlikely(value == 0)) {
80 msb = fls(value) - 1;
87 * first y is determined by shifting the value left
96 significand = value << (31 - msb);
107 * needed value for next table entry is 0x800000
123 unsigned int intlog10(u32 value) argument
126 * returns: log10(value) *
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/drivers/media/pci/cx25821/
H A Dcx25821-biffuncs.h33 static inline u32 clearBitAtPos(u32 value, u8 bit) argument
35 return value & ~(1 << bit);
/drivers/net/ethernet/altera/
H A Daltera_utils.c22 u32 value = csrrd32(ioaddr, offs); local
23 value |= bit_mask;
24 csrwr32(value, ioaddr, offs);
29 u32 value = csrrd32(ioaddr, offs); local
30 value &= ~bit_mask;
31 csrwr32(value, ioaddr, offs);
36 u32 value = csrrd32(ioaddr, offs); local
37 return (value & bit_mask) ? 1 : 0;
42 u32 value = csrrd32(ioaddr, offs); local
43 return (value
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/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_xpcs.c21 u32 value; local
24 value = readl(priv->ioaddr + XPCS_OFFSET + reg);
26 return value;
40 u32 value; local
42 value = sxgbe_xpcs_read(ndev, SR_PCS_MMD_CONTROL1);
46 sxgbe_xpcs_write(ndev, VR_PCS_MMD_XAUI_MODE_CONTROL, value | BIT(13));
47 sxgbe_xpcs_write(ndev, SR_PCS_MMD_CONTROL1, value | BIT(11));
50 value = sxgbe_xpcs_read(ndev, VR_PCS_MMD_DIGITAL_STATUS);
51 } while ((value & XPCS_QSEQ_STATE_MPLLOFF) == XPCS_QSEQ_STATE_STABLE);
53 value
65 int value; local
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/drivers/staging/android/uapi/
H A Dsw_sync.h21 __u32 value; member in struct:sw_sync_create_fence_data
/drivers/bcma/
H A Ddriver_chipcommon_b.c15 u32 value, int timeout)
22 if ((val & mask) == value)
33 void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value) argument
39 writel(value, ccb->mii + 0x04);
14 bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask, u32 value, int timeout) argument
/drivers/cpufreq/
H A Dppc_cbe_cpufreq_pervasive.c58 u64 value; local
78 value = in_be64(&pmd_regs->pmcr);
80 value &= 0xFFFFFFFFFFFFFFF8ull;
82 value |= pmode;
84 out_be64(&pmd_regs->pmcr, value);
88 value = in_be64(&pmd_regs->pmsr) & 0x07;
89 while (value != pmode) {
91 value = in_be64(&pmd_regs->pmsr) & 0x07;
/drivers/gpio/
H A Dgpio-sa1100.c22 static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) argument
24 if (value)
40 static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value) argument
45 sa1100_gpio_set(chip, offset, value);
H A Dgpio-twl6040.c50 int value)
56 static void twl6040gpo_set(struct gpio_chip *chip, unsigned offset, int value) argument
66 if (value)
49 twl6040gpo_direction_out(struct gpio_chip *chip, unsigned offset, int value) argument
/drivers/gpu/drm/nouveau/core/engine/software/
H A Dnv50.h32 u32 value; member in struct:nv50_software_chan::__anon832

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