/drivers/video/fbdev/ |
H A D | maxinefb.c | 67 unsigned char *wptr; local 69 wptr = regs + 0xa0000 + (regno << 4); 71 *((volatile unsigned short *) (wptr)) = val;
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/drivers/media/usb/pvrusb2/ |
H A D | pvrusb2-debugifc.c | 69 const char *wptr; local 74 wptr = NULL; 82 wptr = buf; 87 *wstrPtr = wptr; 198 const char *wptr; local 202 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); 205 if (!wptr) return 0; 207 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr); 208 if (debugifc_match_keyword(wptr,wlen,"reset")) { 209 scnt = debugifc_isolate_word(buf,count,&wptr, [all...] |
/drivers/gpu/drm/msm/adreno/ |
H A D | adreno_gpu.c | 108 adreno_gpu->memptrs->wptr = 0; 191 uint32_t wptr = get_wptr(gpu->rb); local 196 gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr); 202 uint32_t wptr = get_wptr(gpu->rb); local 205 if (spin_until(adreno_gpu->memptrs->rptr == wptr)) 225 seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); 226 seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb)); 261 printk("wptr: %d\n", adreno_gpu->memptrs->wptr); 282 uint32_t wptr = get_wptr(gpu->rb); local [all...] |
H A D | adreno_gpu.h | 55 volatile uint32_t wptr; member in struct:adreno_rbmemptrs 73 /* ringbuffer rptr/wptr: */
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/drivers/gpu/drm/radeon/ |
H A D | radeon_ring.c | 38 * GPU is currently reading, and a wptr (write pointer) 42 * wptr. The GPU then starts fetching commands and executes 84 ring->ring_free_dw -= ring->wptr; 125 ring->wptr_old = ring->wptr; 161 * Update the wptr (write pointer) to tell the GPU to 173 while (ring->wptr & ring->align_mask) { 203 * radeon_ring_undo - reset the wptr 207 * Reset the driver's copy of the wptr (all asics). 211 ring->wptr = ring->wptr_old; 215 * radeon_ring_unlock_undo - reset the wptr an 468 uint32_t rptr, wptr, rptr_next; local [all...] |
H A D | ni.c | 1384 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; 1444 u32 wptr; local 1447 wptr = RREG32(CP_RB0_WPTR); 1449 wptr = RREG32(CP_RB1_WPTR); 1451 wptr = RREG32(CP_RB2_WPTR); 1453 return wptr; 1460 WREG32(CP_RB0_WPTR, ring->wptr); 1463 WREG32(CP_RB1_WPTR, ring->wptr); 1466 WREG32(CP_RB2_WPTR, ring->wptr); 1666 ring->wptr [all...] |
H A D | r600.c | 2553 u32 wptr; local 2555 wptr = RREG32(R600_CP_RB_WPTR); 2557 return wptr; 2563 WREG32(R600_CP_RB_WPTR, ring->wptr); 2667 ring->wptr = 0; 2668 WREG32(CP_RB_WPTR, ring->wptr); 3262 next_rptr = ring->wptr + 3 + 4; 3268 next_rptr = ring->wptr + 5 + 4; 3346 * increments the rptr. When the rptr catches up with the wptr, all the 3495 /* set rptr, wptr t 3920 u32 wptr, tmp; local 3975 u32 wptr; local [all...] |
H A D | evergreen.c | 2800 next_rptr = ring->wptr + 3 + 4; 2806 next_rptr = ring->wptr + 5 + 4; 2958 ring->wptr = 0; 2959 WREG32(CP_RB_WPTR, ring->wptr); 4745 u32 wptr, tmp; local 4748 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 4750 wptr = RREG32(IH_RB_WPTR); 4752 if (wptr & RB_OVERFLOW) { 4753 wptr &= ~RB_OVERFLOW; 4755 * from the last not overwritten vector (wptr 4770 u32 wptr; local [all...] |
H A D | r100.c | 1062 u32 wptr; local 1064 wptr = RREG32(RADEON_CP_RB_WPTR); 1066 return wptr; 1072 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1172 ring->wptr = 0; 1173 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 2986 seq_printf(m, "Ring wptr %u\n", r_wptr); 2988 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2990 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 3671 u32 next_rptr = ring->wptr [all...] |
H A D | si.c | 3379 next_rptr = ring->wptr + 3 + 4 + 8; 3385 next_rptr = ring->wptr + 5 + 4 + 8; 3639 ring->wptr = 0; 3640 WREG32(CP_RB0_WPTR, ring->wptr); 3670 ring->wptr = 0; 3671 WREG32(CP_RB1_WPTR, ring->wptr); 3694 ring->wptr = 0; 3695 WREG32(CP_RB2_WPTR, ring->wptr); 5885 /* set rptr, wptr to 0 */ 5999 /* set rptr, wptr t 6320 u32 wptr, tmp; local 6355 u32 wptr; local [all...] |
/drivers/net/ppp/ |
H A D | ppp_deflate.c | 193 unsigned char *wptr; local 207 wptr = obuf; 212 wptr[0] = PPP_ADDRESS(rptr); 213 wptr[1] = PPP_CONTROL(rptr); 214 put_unaligned_be16(PPP_COMP, wptr + 2); 215 wptr += PPP_HDRLEN; 216 put_unaligned_be16(state->seqno, wptr); 217 wptr += DEFLATE_OVHD; 219 state->strm.next_out = wptr;
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H A D | bsd_comp.c | 580 unsigned char *wptr; local 586 if (wptr) \ 588 *wptr++ = (unsigned char) (v); \ 591 wptr = NULL; \ 630 wptr = obuf; 639 if (wptr) 641 *wptr++ = PPP_ADDRESS(rptr); 642 *wptr++ = PPP_CONTROL(rptr); 643 *wptr++ = 0; 644 *wptr 843 unsigned char *wptr; local [all...] |
/drivers/infiniband/hw/cxgb3/ |
H A D | cxio_hal.h | 68 u32 wptr; member in struct:cxio_hal_ctrl_qp
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H A D | cxio_hal.c | 435 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n", 608 PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n", 609 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len, 613 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr, 617 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i); 620 rdev_p->ctrl_qp.wptr, 629 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % 671 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % 674 /* wptr in the WRID[31:0] */ 675 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr; 706 u32 wptr; local 767 u32 wptr; local 1120 u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2); local [all...] |
H A D | cxio_wr.h | 46 #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr)) 47 #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \ 48 ((rptr)!=(wptr)) ) 50 #define Q_FREECNT(rptr,wptr,size_log2) ((1UL<<size_log2)-((wptr)-(rptr))) 51 #define Q_COUNT(rptr,wptr) ((wptr)-(rptr)) 697 u32 wptr; /* id member in struct:t3_wq 718 u32 wptr; member in struct:t3_cq [all...] |
/drivers/staging/media/lirc/ |
H A D | lirc_parallel.c | 85 static unsigned int wptr; variable 210 nwptr = (wptr + 1) & (RBUF_SIZE - 1); 217 rbuf[wptr] = signal; 218 wptr = nwptr; 338 if (rptr != wptr) { 457 if (rptr != wptr) 524 wptr = 0;
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/drivers/tty/serial/ |
H A D | men_z135_uart.c | 294 u32 wptr; local 316 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); 317 txc = (wptr >> 16) & 0x3ff; 318 wptr &= 0x3ff; 333 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr)) 334 n = 4 - BYTES_TO_ALIGN(wptr); 445 u32 wptr; local 448 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); 449 txc = (wptr >> 16) & 0x3ff;
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/drivers/scsi/ |
H A D | qla1280.c | 608 uint16_t *wptr; local 620 wptr = (uint16_t *)&ha->nvram; 624 *wptr = qla1280_get_nvram_word(ha, cnt); 625 chksum += *wptr & 0xff; 626 chksum += (*wptr >> 8) & 0xff; 627 wptr++; 636 *wptr = qla1280_get_nvram_word(ha, cnt); 637 chksum += *wptr & 0xff; 638 chksum += (*wptr >> 8) & 0xff; 639 wptr 3421 uint16_t *wptr; local [all...] |
/drivers/scsi/qla2xxx/ |
H A D | qla_isr.c | 266 uint16_t __iomem *wptr; local 281 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1); 285 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8); 287 ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr); 289 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 291 wptr++; 304 uint16_t __iomem *wptr; local 309 wptr = (uint16_t __iomem *)®24->mailbox1; 311 wptr = (uint16_t __iomem *)®82->mailbox_out[1]; 315 for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr 2452 uint16_t __iomem *wptr; local [all...] |
H A D | qla_mr.c | 2869 uint32_t __iomem *wptr; local 2879 wptr = (uint32_t __iomem *)®->mailbox17; 2882 ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr); 2883 wptr++;
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H A D | qla_sup.c | 550 uint16_t cnt, chksum, *wptr; local 611 wptr = (uint16_t *)req->ring; 614 chksum += le16_to_cpu(*wptr++); 668 uint16_t *wptr; local 689 wptr = (uint16_t *)req->ring; 694 if (*wptr == __constant_cpu_to_le16(0xffff)) 706 chksum += le16_to_cpu(*wptr++); 884 uint16_t *wptr; local 891 wptr = (uint16_t *)req->ring; 895 if (*wptr 983 uint32_t *wptr; local 1035 uint16_t *wptr; local 1325 uint16_t *wptr; local 1365 uint16_t *wptr; local [all...] |
H A D | qla_nx.c | 1986 uint16_t __iomem *wptr; local 1989 wptr = (uint16_t __iomem *)®->mailbox_out[1]; 1996 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); 1997 wptr++;
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/drivers/tty/ |
H A D | moxa.c | 275 u16 rptr, wptr, mask, len; local 279 wptr = readw(ofsAddr + RXwptr); 281 len = (wptr - rptr) & mask; 1997 u16 rptr, wptr, mask; local 2000 wptr = readw(ofsAddr + TXwptr); 2002 return (wptr - rptr) & mask; 2008 u16 rptr, wptr, mask; local 2011 wptr = readw(ofsAddr + TXwptr); 2013 return mask - ((wptr - rptr) & mask); 2019 u16 rptr, wptr, mas local [all...] |
/drivers/net/ethernet/tehuti/ |
H A D | tehuti.h | 146 u32 rptr, wptr; /* cached values of RPTR and WPTR registers, member in struct:fifo 202 struct tx_map *wptr; /* points to the next element to write */ member in struct:txdb
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/drivers/net/ethernet/micrel/ |
H A D | ks8851_mll.c | 544 * @wptr: buffer address to save data 548 static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len) argument 552 *wptr++ = (u16)ioread16(ks->hw_addr); 558 * @wptr: buffer address 562 static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len) argument 566 iowrite16(*wptr++, ks->hw_addr);
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