Searched refs:PHYS_OFFSET (Results 26 - 50 of 50) sorted by relevance

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/arch/arm/kernel/
H A Dhead-nommu.S71 ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET
191 * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
216 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET
219 setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled
221 setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
H A Dsetup.c683 if (aligned_start < PHYS_OFFSET) {
684 if (aligned_start + size <= PHYS_OFFSET) {
685 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
690 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
691 aligned_start, (u64)PHYS_OFFSET);
693 size -= PHYS_OFFSET - aligned_start;
694 aligned_start = PHYS_OFFSET;
734 start = PHYS_OFFSET;
H A Datags_compat.c159 tag = memtag(tag, PHYS_OFFSET + (i << 26),
163 tag = memtag(tag, PHYS_OFFSET, params->u1.s.nr_pages * PAGE_SIZE);
H A Datags_parse.c189 default_tags.mem.start = PHYS_OFFSET;
H A Dhead.S111 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
112 add r8, r8, r4 @ PHYS_OFFSET
575 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
584 subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
590 str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
/arch/arm/mach-keystone/
H A Dkeystone.c69 phys_addr_t offset = PHYS_OFFSET - KEYSTONE_LOW_PHYS_START;
/arch/hexagon/kernel/
H A Dsetup.c68 printk(KERN_INFO "PHYS_OFFSET=0x%08x\n", PHYS_OFFSET);
/arch/unicore32/kernel/
H A Dhead.S23 #if (PHYS_OFFSET & 0x003fffff)
24 #error "PHYS_OFFSET must be at an even 4MiB boundary!"
28 #define KERNEL_RAM_PADDR (PHYS_OFFSET + KERNEL_IMAGE_START)
123 or r6, r7, #(PHYS_OFFSET & 0xffc00000)
H A Dsetup.c184 start = PHYS_OFFSET;
/arch/hexagon/mm/
H A Dinit.c34 #define bootmem_startpg (PFN_UP(((unsigned long) _end) - PAGE_OFFSET + PHYS_OFFSET))
/arch/arm/mach-tegra/
H A Dpm.c198 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
343 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
/arch/arm/mm/
H A Dnommu.c91 phys_addr_t phys_offset = PHYS_OFFSET;
102 * PHYS_OFFSET */
104 panic("First memory bank must be contiguous from PHYS_OFFSET");
126 pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
263 region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
H A Dmmap.c196 if (addr < PHYS_OFFSET)
H A Dproc-v7-3level.S132 cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET?
140 * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
H A Dinit.c178 arm_dma_limit = PHYS_OFFSET + arm_dma_zone_size - 1;
537 free_reserved_area(__va(PHYS_OFFSET), swapper_pg_dir, -1, NULL);
H A Dmmu.c1240 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
/arch/arm/plat-iop/
H A Dpci.c236 *IOP3XX_IABAR2 = PHYS_OFFSET |
240 *IOP3XX_IATVR2 = PHYS_OFFSET;
/arch/mips/mti-malta/
H A Dmalta-init.c254 mask = PHYS_OFFSET | (1<<3);
257 mask = PHYS_OFFSET;
H A Dmalta-memory.c91 mdesc[0].base = PHYS_OFFSET;
/arch/arm/mach-clps711x/
H A Dboard-edb7211.c134 memblock_reserve(PHYS_OFFSET, VIDEORAM_SIZE);
H A Dboard-p720t.c314 tag->u.mem.start = PHYS_OFFSET;
/arch/arm/mach-iop13xx/
H A Dpci.c571 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
576 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
583 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
740 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
745 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
752 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
/arch/arm/mach-iop13xx/include/mach/
H A Diop13xx.h83 #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
104 #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
/arch/arm64/mm/
H A Dmmu.c416 * PHYS_OFFSET (which must be aligned to 2MB as per
420 limit = PHYS_OFFSET + PMD_SIZE;
422 limit = PHYS_OFFSET + PUD_SIZE;
/arch/mips/include/asm/
H A Dio.h138 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);

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