/arch/arm/mm/ |
H A D | cache-xsc3l2.c | 56 int set, way; local 60 for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) { 62 set_way = (way << 29) | (set << 5); 161 * optimize L2 flush all operation by set/way format 166 int set, way; local 170 for (set = 0; set < CACHE_SET_SIZE(l2ctype); set [all...] |
H A D | dump.c | 3 * so that we can see what the various memory ranges are set to. 50 const char *set; member in struct:prot_bits 58 .set = "USR", 63 .set = "ro", 68 .set = "NX", 73 .set = "SHD", 78 .set = "SO/UNCACHED", 82 .set = "MEM/BUFFERABLE/WC", 86 .set = "MEM/CACHED/WT", 90 .set [all...] |
/arch/x86/crypto/ |
H A D | aes_ctrby8_avx-x86_64.S | 159 .set by, \b 160 .set load_keys, \k 161 .set klen, \key_len 169 .set i, 1 180 .set i, (i +1) 193 .set i, 1 197 .set i, (i +1) 202 .set i, 0 206 .set i, (i +1) 217 .set [all...] |
H A D | sha1_ssse3_asm.S | 3 * SSE3 instruction set extensions introduced in Intel Core Microarchitecture 124 .set i, 0 127 .set i, (i+1) 196 .set A, REG_A 197 .set B, REG_B 198 .set C, REG_C 199 .set D, REG_D 200 .set E, REG_E 201 .set T1, REG_T1 202 .set T [all...] |
/arch/mips/include/asm/ |
H A D | asm.h | 99 .set push; \ 100 .set reorder; \ 104 .set pop; \ 112 .set push; \ 113 .set reorder; \ 116 .set pop; \ 140 * Use with .set noreorder only! 148 .set push; \ 149 .set arch=r5000; \ 151 .set po [all...] |
H A D | stackframe.h | 29 .set push 30 .set noat 32 .set pop 147 .set push 148 .set noat 149 .set reorder 152 .set noreorder 155 .set reorder 162 .set at=k0 164 .set noa [all...] |
H A D | pm.h | 44 .set push 45 .set noreorder 64 .set pop 113 .set push 114 .set noreorder 119 .set pop
|
/arch/mips/lib/ |
H A D | strlen_user.S | 52 .set __strlen_user_asm, __strlen_kernel_asm 53 .set __strlen_user_nocheck_asm, __strlen_kernel_nocheck_asm 60 .set push 61 .set eva 63 .set pop
|
H A D | strncpy_user.S | 73 .set __strncpy_from_user_asm, __strncpy_from_kernel_asm 74 .set __strncpy_from_user_nocheck_asm, __strncpy_from_kernel_nocheck_asm 80 .set push 81 .set eva 83 .set pop
|
H A D | memset.S | 80 .set noreorder 91 .set __memset, 1 107 .set noat 111 .set at 130 .set reorder 135 .set noreorder 146 .set noat 149 .set at 154 .set push 155 .set noreorde [all...] |
/arch/xtensa/variants/dc233c/include/variant/ |
H A D | tie-asm.h | 66 * continue If macro invoked as part of a larger store sequence, set to 1 84 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 87 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 96 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 99 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 114 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 117 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 130 * continue If macro invoked as part of a larger load sequence, set to 1 148 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 151 .set [all...] |
/arch/arm/plat-samsung/include/plat/ |
H A D | pm.h | 74 * @set: set bits for the state of the LEDs 77 extern void s3c_pm_debug_smdkled(u32 set, u32 clear); 80 static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { } argument 84 * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
|
/arch/mips/bcm63xx/ |
H A D | clk.c | 20 void (*set)(struct clk *, int); member in struct:clk 31 if (clk->set && (clk->usage++) == 0) 32 clk->set(clk, 1); 37 if (clk->set && (--clk->usage) == 0) 38 clk->set(clk, 0); 73 .set = enet_misc_set, 100 .set = enetx_set, 105 .set = enetx_set, 119 .set = ephy_set, 149 .set [all...] |
/arch/alpha/lib/ |
H A D | strchr.S | 11 .set noreorder 12 .set noat 28 cmpbge zero, t0, t2 # .. e1 : bits set iff byte == zero 32 cmpbge zero, t4, t4 # .. e1 : bits set iff byte is garbage 35 cmpbge zero, t1, t3 # e0 : bits set iff byte == c 36 or t2, t3, t0 # e1 : bits set iff char match or zero match 44 cmpbge zero, t0, t2 # e0 : bits set iff byte == 0 45 cmpbge zero, t1, t3 # .. e1 : bits set iff byte == c 49 $found: negq t0, t1 # e0 : clear all but least set bit 52 and t0, t3, t1 # e0 : bit set if [all...] |
H A D | dbg_current.S | 11 .set noat
|
H A D | dbg_stackcheck.S | 11 .set noat
|
H A D | strncat.S | 22 mov $16, $0 # set up return value 32 cmpbge $31, $1, $2 # bits set iff byte == 0 40 $found: negq $2, $3 # clear all but least set bit 43 and $2, 0xf0, $3 # binary search for that set bit
|
H A D | ev67-strchr.S | 21 .set noreorder 22 .set noat 48 cmpbge zero, t0, t2 # E : bits set iff byte == zero 49 cmpbge zero, t4, t4 # E : bits set iff byte is garbage 54 cmpbge zero, t1, t3 # E : bits set iff byte == c 55 or t2, t3, t0 # E : bits set iff char match or zero match 71 cmpbge zero, t0, t2 # E : bits set iff byte == 0 73 cmpbge zero, t1, t3 # E : bits set iff byte == c 78 $found: negq t0, t1 # E : clear all but least set bit 80 and t0, t3, t1 # E : bit set if [all...] |
/arch/arm/kernel/ |
H A D | io.c | 14 void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set) argument 21 value |= (set & mask); 27 void atomic_io_modify(void __iomem *reg, u32 mask, u32 set) argument 34 value |= (set & mask);
|
/arch/mips/ath79/ |
H A D | common.h | 29 void ath79_gpio_function_setup(u32 set, u32 clear);
|
/arch/unicore32/include/asm/ |
H A D | hwdef-copro.h | 44 extern void adjust_cr(unsigned long mask, unsigned long set);
|
/arch/sh/lib/ |
H A D | movmem.S | 45 .set __movstr, __movmem 83 .set __movstrSI64, __movmemSI64 89 .set __movstrSI60, __movmemSI60 95 .set __movstrSI56, __movmemSI56 101 .set __movstrSI52, __movmemSI52 107 .set __movstrSI48, __movmemSI48 113 .set __movstrSI44, __movmemSI44 119 .set __movstrSI40, __movmemSI40 125 .set __movstrSI36, __movmemSI36 131 .set __movstrSI3 [all...] |
/arch/m68k/fpsp040/ |
H A D | kernel_ex.S | 7 | set the appropriate bits in the USER_FPSR word on the stack. 51 | set FPSR exception status dz bit, condition code 57 | set exception status bit & accrued bits in FPSR 58 | set flag to disable sto_res from corrupting fp register 67 bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR 68 fmovel #0,%FPSR |clr status bits (Z set) 73 fmovel #0,%FPSR |clr status bits (Z set) 84 bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR 89 orl #dzinf_mask,USER_FPSR(%a6) |set I,DZ,ADZ 97 bsetb #neg_bit,FPSR_CC(%a6) |set ne [all...] |
/arch/sparc/kernel/ |
H A D | trampoline_32.S | 45 set (PSR_PIL | PSR_S | PSR_PS), %g1 59 set current_set, %g5 74 set poke_srmmu, %g5 99 set (PSR_PIL | PSR_S | PSR_PS), %g1 109 set trapbase, %g1 114 set SUN4D_BOOTBUS_CPUID, %g3 121 set current_set, %g5 135 set poke_srmmu, %g5 151 set smp_penguin_ctable,%g1 154 set [all...] |
/arch/mips/kernel/ |
H A D | r4k_fpu.S | 22 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ 26 .set push 28 .set nomacro 30 .set pop 36 .set noreorder 37 .set arch=r4000 40 .set push 43 .set pop 46 .set push 49 .set mips32r [all...] |