Searched refs:set (Results 251 - 275 of 536) sorted by relevance

<<11121314151617181920>>

/arch/arm/mach-omap1/
H A Dams-delta-fiq-handler.S101 ldr r12, omap_ih1_base @ set pointer to level1 handler
127 ldr r12, omap1510_gpio_base @ set base pointer to GPIO bank
138 ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set?
178 orreq r8, r8, r10 @ set 1 at current mask position
223 tst r13, #HOOK_SWITCH_MASK @ is hook switch status bit set?
240 tst r13, #MODEM_IRQ_MASK @ is modem status bit set?
255 ldr r12, deferred_fiq_ih_base @ set pointer to IRQ handler
256 mov r10, #DEFERRED_FIQ_MASK @ set deferred_fiq bit
259 ldr r12, omap1510_gpio_base @ set pointer back to GPIO bank
/arch/arm/mm/
H A Dproc-arm940.S296 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
306 orr r0, r0, #1 @ set enable bit
307 mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
317 orr r0, r0, #1 @ set enable bit
318 mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
H A Dproc-v6.S107 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
114 mcr p15, 0, r1, c13, c0, 1 @ set context ID
160 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
227 orr r0, r0, r6 @ set them
240 orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
H A Dproc-arm946.S343 mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
352 orr r0, r0, #1 @ set enable bit
353 mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM
362 orr r0, r0, #1 @ set enable bit
363 mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH
386 mcr p15, 0, r0, c5, c0, 2 @ set data access permission
387 mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
/arch/cris/arch-v10/kernel/
H A Ddebugport.c51 IO_STATE(R_IRQ_MASK1_SET, ser0_data, set),
65 IO_STATE(R_IRQ_MASK1_SET, ser1_data, set),
79 IO_STATE(R_IRQ_MASK1_SET, ser2_data, set),
93 IO_STATE(R_IRQ_MASK1_SET, ser3_data, set),
373 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
/arch/ia64/kernel/
H A Dptrace.c44 * is (instruction set; one bit)
49 #define MASK(nbits) ((1UL << (nbits)) - 1) /* mask with NBITS bits set */
71 * bitset where bit i is set iff the NaT bit of register i is set.
242 * backing store, rnat0/rnat1 are set to 0 and the low order bits are
326 * If entered via syscall, don't allow user to set rnat bits
794 dprintk("ptrace: failed to set ar.unat\n");
1022 /* NaT bit will be set via PT_NAT_BITS: */
1134 /* make sure the single step/taken-branch trap bits are not set: */
1143 * Make sure the single step bit is not set
1263 struct regset_set set; member in union:regset_getset::__anon1774
[all...]
/arch/m68k/fpsp040/
H A Dx_operr.S216 orl #opaop_mask,USER_FPSR(%a6) |set operr & aiop
224 | set by the 040.
227 orl #opaop_mask,USER_FPSR(%a6) |set operr & aiop
285 | to d0 for write out. If not, it is a real operr, and set d0.
322 | operr. If the inex enable bit is set in the FPCR, and either
H A Dssin.S30 | 1. If SIN is invoked, set AdjN := 0; otherwise, set AdjN := 1.
130 .set INARG,FP_SCR4
132 .set X,FP_SCR5
133 .set XDCARE,X+2
134 .set XFRAC,X+4
136 .set RPRIME,FP_SCR1
137 .set SPRIME,FP_SCR2
139 .set POSNEG1,L_SCR1
140 .set TWOTO6
[all...]
/arch/s390/kernel/
H A Dentry64.S100 LPP __SF_EMPTY+16(%r15) # set host id
104 mvi __SF_EMPTY+31(%r15),\reason # set exit reason
284 # _TIF_NEED_RESCHED is set, call schedule
291 # _CIF_MCCK_PENDING is set, call handler
298 # _CIF_ASCE is set, load user space asce
306 # _TIF_SIGPENDING is set, call do_signal
323 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
331 # _TIF_UPROBE is set, call uprobe_notify_resume
341 # _PIF_PER_TRAP is set, call do_per_trap
409 tmhh %r8,0x4000 # PER bit set i
[all...]
/arch/unicore32/mm/
H A Dmmu.c42 * The pmd table for the upper-most set of pages.
61 void adjust_cr(unsigned long mask, unsigned long set) argument
67 set &= mask;
71 cr_no_alignment = (cr_no_alignment & ~mask) | set;
72 cr_alignment = (cr_alignment & ~mask) | set;
74 set_cr((get_cr() & ~mask) | set);
480 * 1. If PG_dcache_clean is not set for the page, we need to ensure
/arch/mips/kernel/
H A Dsignal32.c459 sigset_t set; local
465 if (__copy_conv_sigset_from_user(&set, &frame->rs_uc.uc_sigmask))
468 set_current_blocked(&set);
494 struct pt_regs *regs, sigset_t *set)
504 err |= __copy_conv_sigset_to_user(&frame->sf_mask, set);
534 struct pt_regs *regs, sigset_t *set)
551 err |= __copy_conv_sigset_to_user(&frame->rs_uc.uc_sigmask, set);
493 setup_frame_32(void *sig_return, struct ksignal *ksig, struct pt_regs *regs, sigset_t *set) argument
533 setup_rt_frame_32(void *sig_return, struct ksignal *ksig, struct pt_regs *regs, sigset_t *set) argument
/arch/sparc/kernel/
H A Dsignal_32.c67 sigset_t set; local
113 err |= __get_user(set.sig[0], &sf->info.si_mask);
114 err |= __copy_from_user(&set.sig[1], &sf->extramask,
120 set_current_blocked(&set);
133 sigset_t set; local
160 err |= __copy_from_user(&set, &sf->mask, sizeof(sigset_t));
175 set_current_blocked(&set);
541 /* If the current stack was set with sigaltstack, don't
H A Dsignal_64.c43 /* {set, get}context() needed for 64-bit SparcLinux userland. */
66 sigset_t set; local
69 if (__get_user(set.sig[0], &ucp->uc_sigmask.sig[0]))
72 if (__copy_from_user(&set, &ucp->uc_sigmask, sizeof(sigset_t)))
75 set_current_blocked(&set);
253 sigset_t set; local
288 err |= __copy_from_user(&set, &sf->mask, sizeof(sigset_t));
305 set_current_blocked(&set);
/arch/m68k/ifpsp060/src/
H A Dilsp.S96 set POSNEG, -1
97 set NDIVISOR, -2
98 set NDIVIDEND, -3
99 set DDSECOND, -4
100 set DDNORMAL, -8
101 set DDQUOTIENT, -12
102 set DIV64_CC, -16
225 tst.l %d6 # may set 'N' ccode bit
247 ori.w &0x02,DIV64_CC(%a6) # set 'V' ccode bit
277 # signed/unsigned flag ddusign must be set (
[all...]
/arch/arm/boot/dts/
H A Dpicoxcell-pc3x3.dtsi264 regoffset-set = <0x00>;
275 regoffset-set = <0x0c>;
286 regoffset-set = <0x24>;
H A Dpicoxcell-pc3x2.dtsi181 regoffset-set = <0x00>;
192 regoffset-set = <0x0c>;
/arch/arm/lib/
H A Dcopy_template.S86 CALGN( sbcnes r4, r3, r2 ) @ C is always set here
89 CALGN( subs r2, r2, r3 ) @ C gets set
185 CALGN( sbcnes r4, ip, r2 ) @ C is always set here
H A Dmemmove.S51 CALGN( sbcnes r4, ip, r2 ) @ C is always set here
54 CALGN( subs r2, r2, ip ) @ C is set here
135 CALGN( sbcnes r4, ip, r2 ) @ C is always set here
/arch/frv/kernel/
H A Dhead.S280 # rearrange the iomem map and set the protection registers
373 #error No default cache configuration set
400 # set up the runtime environment
444 # set up the exception frame for init
453 ldi.p @(gr29,#4),gr15 ; set current_thread
476 # set up the registers and jump into the kernel
513 subcc gr0,gr0,gr0,icc2 /* set Z, clear C */
572 sub.p gr5,gr6,gr6 ; bit number of highest set bit (1MB=>20)
/arch/powerpc/platforms/52xx/
H A Dmpc52xx_gpt.c51 * responsibility of either the bootloader or the platform setup code to set
349 gpt->gc.set = mpc52xx_gpt_gpio_set;
399 u32 clear, set; local
405 set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
408 set |= MPC52xx_GPT_MODE_WDT_EN;
410 set |= MPC52xx_GPT_MODE_CONTINUOUS;
452 clrsetbits_be32(&gpt->regs->mode, clear, set);
462 * @continuous: set to 1 to make timer continuous free running
701 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
797 /* Make sure GPIOs and IRQs get set u
[all...]
/arch/hexagon/kernel/
H A Dsignal.c107 static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, argument
129 err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
154 * set up the error return value before adding the signal
182 * only set up the rt_frame flavor.
/arch/mn10300/mm/
H A Dcache-flush-by-reg.S66 # set mask
202 # set the mask to cover everything
277 # set the mask
/arch/x86/mm/
H A Dpgtable.c323 * Used to set accessed or dirty bits in the page table entries
327 * set. In that case we do actually need to write the PTE.
436 int set; local
438 set = !test_and_set_bit(_PAGE_BIT_SPLITTING,
440 if (set) {
/arch/arc/mm/
H A Dtlbex.S288 or r0, r0, _PAGE_ACCESSED ; set Accessed Bit
325 ; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
345 or.nz r0, r0, _PAGE_MODIFIED ; if Write, set Dirty bit as well
351 ; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
/arch/arm/kernel/
H A Dhyp-stub.S29 * This is not in .bss, because we set it sufficiently early that the boot-time
117 * Configure HSCTLR to set correct exception endianness/instruction set
128 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
170 mcrne p15, 4, r0, c12, c0, 0 @ set HVBAR
175 * __hyp_set_vectors: Call this after boot to set the initial hypervisor
193 * so you will need to set that to something sensible at the new hypervisor's

Completed in 1055 milliseconds

<<11121314151617181920>>