Searched refs:cache (Results 26 - 50 of 127) sorted by relevance

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/drivers/staging/lustre/lustre/llite/
H A Dxattr_cache.c54 * Initializes xattr cache for an inode.
56 * This initializes the xattr list and marks cache presence.
71 * Find in @cache and return @xattr_name attribute in @xattr,
77 static int ll_xattr_cache_find(struct list_head *cache, argument
85 list_for_each_entry(entry, cache, xe_list) {
109 static int ll_xattr_cache_add(struct list_head *cache, argument
118 if (ll_xattr_cache_find(cache, xattr_name, &xattr) == 0) {
147 list_add(&xattr->xe_list, cache);
162 * This removes an extended attribute from cache.
164 * Remove @xattr_name attribute from @cache
169 ll_xattr_cache_del(struct list_head *cache, const char *xattr_name) argument
200 ll_xattr_cache_list(struct list_head *cache, char *xld_buffer, int xld_size) argument
[all...]
/drivers/net/ethernet/dec/tulip/
H A DKconfig37 own cache lines. Value of 4 corresponds to the typical 32 byte line
39 cache coherence, an example is PowerMac 5500. Otherwise 0 is safe.
64 system cache line size type you are using.
H A Dde4x5.c312 Add cache locks to prevent a race condition as
826 u_long lock; /* Lock the cache accesses */
837 } cache; member in struct:de4x5_private
1144 skb_queue_head_init(&lp->cache.queue);
1145 lp->cache.gepc = GEP_INIT;
1480 /* Test if cache is already locked - requeue skb if so */
1481 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1496 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1520 lp->cache.lock = 0;
1587 if (!test_and_set_bit(0, (void *)&lp->cache
[all...]
H A Dde4x5.h929 if (!lp->useSROM) lp->cache.gep = 0;\
938 lp->cache.gep = (lp->fdx ? 0 : GEP_FDXD);\
939 gep_wr(lp->cache.gep, dev);\
958 if (!lp->useSROM) lp->cache.gep = 0;\
967 lp->cache.gep = (lp->fdx ? 0 : GEP_FDXD) | GEP_MODE;\
968 gep_wr(lp->cache.gep, dev);\
984 lp->cache.gep = (GEP_FDXD | GEP_MODE);\
985 gep_wr(lp->cache.gep, dev);\
/drivers/net/wireless/prism54/
H A Doid_mgt.c244 /* Alloc the cache */
424 void *cache, *_data = data; local
435 cache = priv->mib[n];
436 cache += (cache ? extra * dlen : 0);
441 _data = cache;
444 /* If we are going to write to the cache, we don't want anyone to read
450 if (cache)
462 } else if (!cache)
465 if (cache) {
524 void *cache, *_res = NULL; local
[all...]
/drivers/staging/lustre/lustre/osc/
H A Dosc_page.c96 * Checks an invariant that a page in the cache is covered by a lock, as
225 osc_page_transfer_get(opg, "transfer\0cache");
600 struct cl_client_cache *cache = cli->cl_cache; local
610 if (atomic_read(cli->cl_lru_left) < cache->ccc_lru_max >> 4) {
613 tmp = cache->ccc_lru_max / atomic_read(&cache->ccc_users);
781 * reasons: redirtied or deleted from page cache. */
821 struct cl_client_cache *cache = cli->cl_cache; local
825 LASSERT(cache != NULL);
826 LASSERT(!list_empty(&cache
[all...]
/drivers/infiniband/core/
H A DMakefile12 device.o fmr_pool.o cache.o netlink.o
/drivers/net/wireless/cw1200/
H A Dtxrx.h42 struct tx_policy_cache_entry cache[TX_POLICY_CACHE_SIZE]; member in struct:tx_policy_cache
45 spinlock_t lock; /* Protect policy cache */
49 /* TX policy cache */
50 /* Intention of TX policy cache is an overcomplicated WSM API.
/drivers/oprofile/
H A Dcpu_buffer.h17 #include <linux/cache.h>
/drivers/pci/
H A Dsetup-irq.c17 #include <linux/cache.h>
/drivers/usb/core/
H A Dquirks.c215 struct usb_interface_cache *cache; local
218 cache = cfg->intf_cache[j];
219 if (cache->num_altsetting == 0)
222 intf = &cache->altsetting[0];
/drivers/video/fbdev/
H A Dsh_mobile_lcdcfb.h63 void *cache; member in struct:sh_mobile_lcdc_chan
/drivers/net/ethernet/mellanox/mlx5/core/
H A Dcmd.c1081 if (msg->cache) {
1082 spin_lock_irqsave(&msg->cache->lock, flags);
1083 list_add_tail(&msg->list, &msg->cache->head);
1084 spin_unlock_irqrestore(&msg->cache->lock, flags);
1169 ent = &cmd->cache.large;
1171 ent = &cmd->cache.med;
1272 list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1277 list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1290 spin_lock_init(&cmd->cache.large.lock);
1291 INIT_LIST_HEAD(&cmd->cache
[all...]
/drivers/gpu/drm/shmobile/
H A Dshmob_drm_crtc.c271 /* Disable the MERAM cache. */
272 if (scrtc->cache) {
273 sh_mobile_meram_cache_free(sdev->meram, scrtc->cache);
274 scrtc->cache = NULL;
324 if (scrtc->cache)
325 sh_mobile_meram_cache_update(sdev->meram, scrtc->cache,
383 void *cache; local
396 /* Enable MERAM cache if configured. We need to de-init
399 if (scrtc->cache) {
400 sh_mobile_meram_cache_free(sdev->meram, scrtc->cache);
[all...]
/drivers/net/wireless/rt2x00/
H A Drt2x00usb.c97 if (unlikely(!rt2x00dev->csr.cache || buffer_length > CSR_CACHE_SIZE)) {
98 rt2x00_err(rt2x00dev, "CSR cache not available\n");
103 memcpy(rt2x00dev->csr.cache, buffer, buffer_length);
106 offset, 0, rt2x00dev->csr.cache,
110 memcpy(buffer, rt2x00dev->csr.cache, buffer_length);
763 kfree(rt2x00dev->csr.cache);
764 rt2x00dev->csr.cache = NULL;
769 rt2x00dev->csr.cache = kzalloc(CSR_CACHE_SIZE, GFP_KERNEL);
770 if (!rt2x00dev->csr.cache)
/drivers/infiniband/hw/qib/
H A Dqib_qsfp.h179 struct qib_qsfp_cache cache; member in struct:qib_qsfp_data
/drivers/iommu/
H A Dtegra-smmu.c102 #define __SMMU_CACHE_CONFIG(mc, cache) (SMMU_CACHE_CONFIG_BASE + 4 * cache)
103 #define SMMU_CACHE_CONFIG(cache) __SMMU_CACHE_CONFIG(_MC, cache)
145 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss) \
146 (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
291 int cache; member in struct:smmu_debugfs_info
1002 offs = SMMU_CACHE_CONFIG(info->cache);
1044 offs = SMMU_STATS_CACHE_COUNT(info->mc, info->cache, i);
1100 struct dentry *cache; local
[all...]
H A Dshmobile-iommu.c51 struct kmem_cache *cache, size_t size)
53 pgtable->pgtable = kmem_cache_zalloc(cache, GFP_ATOMIC);
62 struct kmem_cache *cache, size_t size)
65 kmem_cache_free(cache, pgtable->pgtable);
50 pgtable_alloc(struct shmobile_iommu_domain_pgtable *pgtable, struct kmem_cache *cache, size_t size) argument
61 pgtable_free(struct shmobile_iommu_domain_pgtable *pgtable, struct kmem_cache *cache, size_t size) argument
/drivers/md/bcache/
H A Dsuper.c40 /* Default is -1; we skip past it for struct cached_dev's cache mode */
189 err = "Bad cache device number in set";
295 struct cache *ca = bio->bi_private;
311 struct cache *ca;
496 * lru (and in the future other) cache replacement policies; for most purposes
517 struct cache *ca = bio->bi_private;
524 static void prio_io(struct cache *ca, uint64_t bucket, unsigned long rw)
544 void bch_prio_write(struct cache *ca)
610 static void prio_read(struct cache *ca, uint64_t bucket)
686 struct cache *c
[all...]
H A Dio.c154 void bch_count_io_errors(struct cache *ca, int error, const char *m)
210 struct cache *ca = PTR_CACHE(c, &b->key, 0);
H A Djournal.c20 * them into the cache in precisely the same order as they appear in the
33 static int journal_read_bucket(struct cache *ca, struct list_head *list,
155 struct cache *ca;
408 struct cache *ca = container_of(ja, struct cache, journal);
424 static void do_journal_discard(struct cache *ca)
470 struct cache *ca;
583 struct cache *ca;
649 closure_bio_submit(bio, cl, c->cache[0]);
H A Dmovinggc.c193 static unsigned bucket_heap_top(struct cache *ca)
201 struct cache *ca;
/drivers/block/drbd/
H A DKconfig35 cache coherency.
/drivers/bus/
H A DKconfig50 Driver supporting the CCI cache coherent interconnect for ARM
/drivers/dma/
H A Ddmaengine.c956 struct kmem_cache *cache; member in struct:dmaengine_unmap_pool
1033 if (p->cache)
1034 kmem_cache_destroy(p->cache);
1035 p->cache = NULL;
1050 p->cache = kmem_cache_create(p->name, size, 0,
1052 if (!p->cache)
1054 p->pool = mempool_create_slab_pool(1, p->cache);

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